Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction Hao Yu and Lei He Electrical Engineering Dept. UCLA http//:eda.ee.ucla.edu This work is sponsored by SRC grant (1100.001) Research Projects Overview

Crosstalk Introduce Delay Variability Capacitive coupling introduces local ac current-path and changes delay due to Miller effect Inductive coupling introduces long-range ac current-path and further brings delay variation They could be both controlled by providing local return-path such as shielding or in a ‘GSG’ structure such as co-planar wire (CO) S G S2 S1 via Coplanar T-lines Silicon substrate Micro-strip T-lines Research Projects Overview

Structured Predictable Interconnect Regular Dense Wire Fabric: Morton DAC’99, LSI IEDM’02 Power grid Ground grid Via (connect shield) Signal net Shield net Cross-under Power grid acts as ground lines, and cross-under further reduces coupling Wide signal line is split into several narrow wires Increase in area and overall capacitance, and mutual inductance is not significantly reduced Increase in delay variation for multiple signal lines signal one shielding [Sato:ISQED’03] The shielding is not uniform distributed Research Projects Overview

Interconnect Design Considering Inductance Control/design the return path to reduce self-inductance Reducing signal oscillation requires the smallest overall loop inductance Return to ground as near as possible, i.e., ground lines need to be close to signal lines Reducing delay variation requires each signal line to have a similar self loop inductance Return paths need uniformly distributed, i.e., a biased design of ground lines is not preferred Research Projects Overview

Interconnect Design Considering Inductance Control and design a wiring pattern to reduce mutual-inductance Reducing long-range crosstalk needs to cancel mutual coupled magnetic flux Twisted and normal wire (TN) Twist signal lines with shielding to form polarity-interleaved flux [Zhong:ICCAD’00] Need additional normal wires to reduce mutual inductance The mutual coupling between twisted and normal group is reduced The delay/crosstalk in normal group is still big and varied for each signal net Research Projects Overview

Technology Aspects of Twisted Interconnect Twisted wire signaling is well-known in wired transmission Telephone line, cable … The challenge of on-chip implementation comes from the cost of vias (Al interconnect) Tungsten plugs has the via resistance as large as 100um wire (Al) Vias Copper is planned in full sub-0.25 um process flows and large-scale designs (IBM and Motorola IEDM’97 IEDM’02) With cladding and other effects, Cu ~ 2.2 mW-cm vs. 3.5 for Al(Cu)  40% reduction in resistance In dual-damascene process via and interconnect are manufactured simultaneously Vias in cooper have reduce resistance as well Research Projects Overview

Our Contribution Twisted and staggered (TS) Measured by a testing chip No normal wire group Reduce both inductive and capacitive coupling uniformly for each signal net Measured by a testing chip TS-interconnect structure reduces delay by 25% and reduces delay variation by 25X compared to coplanar shielding TS-interconnect structure reduces delay by 7.5% and reduces delay variation by 33X compared to TN-interconnect structure Research Projects Overview

Motivation to design twisted wire and staggered twisted-wire Outline Motivation to design twisted wire and staggered twisted-wire Synthesis of twisted bundle by routing matrix Experiment results Conclusion and future work Research Projects Overview

A Twisted Pair A signal wire is twisted with a shield composed of twisted group A normal group (with normal signal and shield wires) is used to achieve a zero mutual inductive coupling [Zhong:ICCAD’02] 0.5 Research Projects Overview

A Low-frequency Model Inductive coupling Capacitive coupling Inductive coupling noise voltage is significantly reduced Capacitive coupling noise voltage is only reduced by a shielding factor α The capacitive coupling length is still large! 0.5*N*l*(1+α) Research Projects Overview

Staggered Twisted Pair Mutual inductive coupling has the similar reduction as no staggering Research Projects Overview

Staggered Twisted Pair Capacitive coupling is reduced Coupling length is reduced by a factor of staggering stage s: 0.5*N*l*(1+α)/s Research Projects Overview

Layout of Twisted Wires dx dy layout for one twist of two signal nets A symmetrical realistic layout for one twisting between signal nets using two layers Achieve uniform delay among each signal net Research Projects Overview

Layout of Twisted Bundle Power grid Ground grid Via (connect shield) Signal net Shield net Cross-under A twist with signal and shield ratio 3:1 Multiple signal wires share with one shielding to reduce the area cost Signal/shield ratio (# of signal nets / # of shield nets) A systematic synthesis of the staggered twisting layout needs to use routing matrix Research Projects Overview

Motivation to design twisted wire and staggered twisted-wire Outline Motivation to design twisted wire and staggered twisted-wire Synthesis of twisted bundle by routing matrix Experiment results Conclusion and future work Research Projects Overview

Routing Matrix Decompose wire segments into four cells: (1) Twisted cell with routing matrix T (2) Complementary twisted cell with routing matrix Tb (3) Normal cell with routing matrix N (4) Complementary normal cell with routing matrix Nb Synthesize each typed group of wire segments according to cyclic permutation Research Projects Overview

An Example Number each wire with [0,1,2,3] Twisted cell with routing matrix T for 3-bit bus with 1 shield Number each wire with [0,1,2,3] 0 represents for the shield Decompose each wire into 4 segments such that it results in a 4x4 array Entry represents each wire segment with wire number Create an initial routing vector T0 A first cyclic permutation of T0 to create a permutation matrix T’ A second cyclic permutation of T’ with inserted 0 element to create routing matrix T Research Projects Overview

Synthesis of Twisted Bundle The permutation matrix is generally feasible for odd number signal net We add one dummy wire when there are even number of signal nets Research Projects Overview

An Example Routing matrix for 12-bit bus with 3:1 signal/shielding ratio Research Projects Overview

Motivation to design twisted wire and staggered twisted-wire Outline Motivation to design twisted wire and staggered twisted-wire Synthesis of twisted bundle by routing matrix Experiment results Conclusion and future work Research Projects Overview

An Accurate Modeling for Twisted Bundle Simple low frequency model can is not accurate at high frequency and can not handle complicated topology of bundles The assumption of return at local shield is inaccurate [Zhong:ICCAD’00] coupling capacitance can act as return path between two adjacent signal nets at high frequency PEEC model for each segment and model reduction by PRIMA to obtain macro-model Research Projects Overview

Macro-model of Structured Interconnect 1-stage 18 signal nets with signal/shield ratio 9:1. The input is a 1.8V exponential voltage source with rising time 50ps 80-pole approximation with 258X speedup (82.9s vs. 20282.41s) All low-order models have non-negligible error Research Projects Overview

Experiment Settings We use 180nm (IBM) and 70nm (Berkeley Predictive Model) We assume that M6 is used to layout the signals and shields The via is chosen as array of the minimum size 0.2um^2 The driver size is about 100X to the minimum inverter size RLC extracted FastHenry/FastCap WCD/WCN determination considering inductance [Chen and He:TCAD’05] Research Projects Overview

Comparison among Structured Interconnect (1) Coplanar Shielding signal (a) 6 bit COPS with signal/shield ratio 3;1 M6 Length: 4000um Width: 0.3um (min Spacing:0.4um (min) Research Projects Overview

Comparison among Structured Interconnect (2) Twisted Bundle Twisted group Normal group (b) 6-bit TWB with signal/shield ratio 3:1 M6 Length: 4000um Width: 0.3um (min) Spacing:0.4um (min) every 1000um for one twist Research Projects Overview

Comparison among Structured Interconnect (3) Staggered Twisted Bundle (c) 6-bit STWB with signal/shield ratio 3:1 M6 Length: 4000um Width: 0.3um (min) Spacing:0.4um (min) every box size is 1000um, and inside the box every 250um for one twist Research Projects Overview

Worst Case Delay/Noise Comparison worst case delay for each signal 10 20 30 40 50 60 1 2 3 4 5 6 signal net number WCD (ps) COPS TWB STWB worst case noise for each signal 0.1 0.2 0.3 0.4 0.5 0.6 1 2 3 4 5 6 signal net number WCN (normalized to Vdd 1.8) COPS TWB STWB STWB has 11ps smaller delay than COPS, and 8ps smaller than TWB STWB has >15% WCN reduction than TWB, and similar WCN as COPS STWB has more uniform WCD/WCN at each signal net Research Projects Overview

Impact of Number of Staggering A small increase of staggering number can reduce both WCD/WCN Staggering becomes saturated as large staggering number results in the parasitic of segmented wire is comparable to via A small number of staggering is preferred as the impact of the process variation from the via is also minimized Research Projects Overview

Impact of Signal/Shielding Ratio Compared to COPS, STWB has Up to 20% WCD reduction Better WCN For large signal/shield ratio Compared to TWB, STWB has 5% and 12% less WCD/WCN value 26% and 28% less WCD/WCN variation Research Projects Overview

Conclusions and Future Work Design of structural interconnect is needed to reduce interconnect capacitance and inductance introduced delay and crosstalk By uniformly distributing shield with twisting A staggered twisted-bundle can achieve the reduction of WCD/WCN A staggered twisted-bundle can achieve a minimum WCD/WCN variability among each signal net A design of test chip is under development based on IBM 0.13um process Research Projects Overview