Pass Transistor Logic Cell Library Group Members: Keith Benson Kofi Inkabi Ashley Nozine

Project Summary Design basic cells that can incorporated into Cadence cell library. Incorporate cells into Cadence’s cell library. Compare technology mapped layout versus CMOS only Layout –Power –Area –Delay

Standard Cell Dimensions

Cell Characteristics 0.25um technology Area *Height * Width Height is constant at 54 = 6.75um Delay *50% Input  50% Output Dynamic Power dissipation *P Dyn = V DD * I ave Iave = (I H  L + I L  H ) / 2

Cell Y2 schematic

Layout without Buffer

Simulation of Layout/no buffer

Cell Y2 no buffer: results

Cell Y2 with buffer schematic

Layout with small buffer

Simulation of Layout/Small Buf.

Cell Y2 small buffer: results

Cell Y2 with buffer*x schematic

Layout with large buffer

Simulation of Layout/Large Buf.

Cell Y2 large buffer: results

Original Schedule A: Project Proposal B: Learn Cadence/Know Cadence Library Specs. C: Build Cell layouts D: Measure Cells for Power, Area, and Power E: Receive Netlist and automatically generate layout of Technology Mapped cells F: Compare Layout of PTL and CMOS cells against CMOS only cells

Revised Schedule A: Locate tool to automatically generate layout from Netlist B: Receive Netlist and automatically generate layout of Technology Mapped cells C: Characterize Technology Mapped layout from netlist D: Characterize CMOS layout from netlist E: Compare Technology Mapped layout vs. CMOS only layout F: Final Report