DSI Division of Integrated Systems Design Applications: Core routers Integrated Systems for Broadband Communications The goal of this research area is to achieve excellence in innovative switch scheduling, packet classification and lookup in a QoS scenario, load- balancing algorithms and backplanes design among others in the networking community. Furthermore, the experience gained for years in VLSI design, together with our know-how in communication systems, establish the basis to provide efficient Network-on-Chip solutions. Access and edge routers Research on standards-based high performance packet switching systems targeted at communications, embedded, wireless and storage applications, that offer flexibility, scalability and end-to-end QoS for routing and switching systems capable of providing from 10 Gbps to 80 Gbps of aggregate user bandwidth. 80 Gbps Intelligent Switch Fabric High performance synchronous switch fabric solution consisting of a scalable serial transceiver, and a 16x16 serial crosspoint switch. Gigabit MultiDrop Switch (GMDS) High performance switch based on a feasible real output queue architecture consisting on a two-chip set and a newly developed multidrop serial link.  Integrated queuing, central scheduling & switching  VOQ planes with independent Unicast/Multicast queuing systems  Aggregate user bandwidth up to 80 Gbps  Sophisticated QoS with 8 priorities  No switch fabric required  8x8 Low speed GMDS prototype proven  Efficient support for QoS, Multi/Broadcast, variable packet size & end-to-end flow control Enterprise backbone switch Storage area networking Multi-service plattforms On-chip networks Goals Intelligent Switches Multiprocessor systems Nowadays intelligent switches offer much more than raw bandwidth and connectivity. The introduction of new applications using different requirements in the scenario of communication networks forces routers and switches, not only to absorb the bandwidth increase, but also to provide different Quality of Services (QoS). Furthermore, the utilization of upcoming gigascale integration, teraflop computing and terabit communication technologies is placing Network-on-Chip (NoC) as a solution to face the demanding challenges due to huge complexity of future telecommunication systems and the increasing design-productivity gap. The research encompasses the development of new architectures for high-performance intelligent gigabit switches, novel scheduling algorithms for VOQ switches with sophisticated QoS mechanisms and the evaluation of new parameters in their performance, the development of new multi-field packet classification architectures for IntServ/DiffServ, priority queuing systems for network processors with QoS support, and area and power efficient QoS architectures for NoC. Proven experience in: Intelligent switches: VOQ switches Multidrop switches QoS support Scheduling algorithms System integration Data networking: Crosspoint switches SDH systems GbE systems Serial backplanes Network-on-chip architectures

DSI Division of Integrated Systems Design Integrated Systems for Broadband Communications 1.6 Gbps Low-Cost 32x32 Crosspoint Switch 32x32 non-blocking crosspoint switch intended for high speed digital data communication applications with Broadcast and Flow-though functions. Research on scalable, adaptable, high-performance, area and power efficient network architectures that satisfy Quality of Service (QoS) requirements at a favourable cost compared with alternative on-chip interconnection approaches. QoS Architectures for Network-on-Chip  Different QoS technologies supported  Distributed deadlock free routing  Distributed routing and congestion/flow control  Low VLSI cost (chip area and power dissipation)  Deep-sub-micron issues  0.5  m GaAs technology  Fully differential serial I/O paths, ECL compatible  Duty cycle distortion ≤ 150 ps  ≤ 2 ps propagation delay for data path  ≤ 250 ps output-to-output skew in Broadcast mode  +3.3 V and -2 V power supplies  256 LDCC package 2.5 Gbps SONET/SDH Terminator Transceiver chipset Integrated 2.5 Gbps section terminator transceiver chipset that allows byte interleaving and de-interleaving four 622 Mbps data buses into a serial 2.5 Gbps output data stream. Evaluation board  0.5  m GaAs technology  Optional scrambling/descrambling  Bit-interleaved parity error  ECL compatible  +3.3 V and -2 V power supplies  192 TBGA package Mesh NoC Data-Networking Network-on-Chip Architectures About DSI The Division of Integrated Systems Design is composed of experienced researchers who are developing commercial products and doing outstanding private and public research in the field of microelectronics since late 80s. The strength of the team is based on its know-how, cutting-edge resources and a set of services which permit to fulfill your company requirements, increasing its competitiveness and international position in new challenging markets. For more information on DSI’s Integrated Systems for Broadband Communications, please contact: © 2004 Division of Integrated Systems Design IUMA Universidad de Las Palmas de Gran Canaria Campus Universitario de Tafira Las Palmas de Gran Canaria, SPAIN Tel: (direct) (reception desk) Fax: URL: