Project ’ s Poster Instructor: Mr. Almog Assaf Real Time Image Processing Presented by: Baruch Koren Shahaf Fisher Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

Entire Project ’ s Goals Preparing a systematic infrastructure for future laboratories projects. Preparing a systematic infrastructure for future laboratories projects. Preparing instructions for integrating new components to this system. Preparing instructions for integrating new components to this system. Studying VHDL language, with an emphasis on coding style, modular and generic design. Studying VHDL language, with an emphasis on coding style, modular and generic design. Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems. Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

The System ’ s Final Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx RGB2YCbCr 24bit 12bit DVI_interface_2rx 1 Clk vsync_out data_en_out hsync_out 24bit block1 YCbCr2RGB Local Bus Gidel ’ s block top_if clk1 clk0 pll4ddrII user_pll clk clk_plus clk_minus ck_a ck_b vsync_in hsync_in data_in (23..0) Contrast_1_comp data_en_in data_out (23..0) Clk ClkClk

DVI interfaces Connection between the DVI Reciever and Transmitter to the FPGA ’ s top level hierarchy. Connection between the DVI Reciever and Transmitter to the FPGA ’ s top level hierarchy. Settings for using default DVI Receiver (SiI1171) operation mode: Settings for using default DVI Receiver (SiI1171) operation mode:  not programmable - with no I2C involve  24-bit pixel data for one pixel per clock Settings for using default DVI Transmitter (SiI1172) operation mode: Settings for using default DVI Transmitter (SiI1172) operation mode:  not programmable - with no I2C involve.  samples one-half pixel (12 bit) at every latch falling and rising edge of the clock. These setting were done at the: DVI_interface_2rx and DVI_interface_2tx blocks. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

Color Space convertions RGB  YCbCr The basic equations to convert between gamma-corrected RGB (notated as R ’ G ’ B ’ ) and YCbCr are: The basic equations to convert between gamma-corrected RGB (notated as R ’ G ’ B ’ ) and YCbCr are: Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

Designing Generic Space Converter – for both RGB2YCbCr and YCbCr2RGB blocks Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

Designing the Contrast_1_component for Dynamic contrast stretching and adaptive gamma correction Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory inputs outputs Contrast_1_component LUT_gamma_0dot5_correction bypass LUT_gamma_1dot0_correction LUT_gamma_2dot5_correction histogram_with_memory controller gamma_sel max_value min_value input_minus_min & max_minus_min manual

Contrast stretching-example Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

Gamma correction (0.4) - example Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory