1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 12/5/2003 Multi-channel Data Acquisition System Mid-Term Presentation

2 Presentation context  Project description. General review  Hardware Block diagram (+Timing and voltage). Process flow. Software General Definition (Main focus on next semester).  Current status.  Planes by Due date.

3 Project Description  For {i=1,I <14,i++} { Analog sampling of Two synchronic signals. Analog sampling of Two synchronic signals. A-D process at accuracy steps of 2.5mv and at 500 kHz frequency. A-D process at accuracy steps of 2.5mv and at 500 kHz frequency. Data will be loaded and filtered at ALTERA FPGA Data will be loaded and filtered at ALTERA FPGA Integrator filter Integrator filter}  Transferring data to Computer.  Controlling commands and viewing threw the computer

4 Data sampler IO PCI bus lines Control data analyzer and synchronize + Memory Main Block diagram Main Block diagram Data line Control lines Main inputs Start sample line

5 Sub block - Data sampler Block diagram Mux 4 ⇨1 Two general purpose inputs (For actions such as battery check..) Main data inputs AD

6 Inputs  Clk1,S – control which of 4 analog inputs(S1A:S4A) will be sampled.  Clk0 – Fall of that signal == start convert. Outputs  DB0:DB11 – Digital signal.  EOC – Digital signal is ready. Sub block - Data sampler Functionality by signals

7 Memory Block ∑ Connector Card Clock generator Controlling logic ESP Sub Block - Control analyzer and memory

8 Computer to ALTERA commands 1. Commands  Reset memory.  Start sampling process  Start data transfer process 2. Signals: 1Byte out of 3bytes used for command 1Byte out of 3bytes used for command Additional 2bits use for hand shack protocol. Additional 2bits use for hand shack protocol.

9 DIO Using DIO in his mode 1 – means 1byte used for hand shacking DIO Connections :  Commands channels -1Byte (Computer via DIO to ALTERA).  Data channel -1 Byte (ALTERA via DIO to computer).  Hand shacking channel - 1Byte. Sub block – Controller analyzer and Memory – DIO Unit

10 2 Triggers signals is used  Trigger out – ALTERA gives a command to external analog signal generator to start.  Trigger in – External signal generator inform that he start's generating the signal Sub block – Controller analyzer and Memory - Trigger signals

11 sampling process – ALTERA controls The flow will be written in VHDL and performed by the ALTERA unit Count =0 Trigger out Is trigger in Clock generate EOC = Rise R (Count) +=D0:12 Count<2048 Count++ Yes No Yes No Yes Done

12 Data transfer to computer Count =0 Port A =R (Count)[0:7] Hand shaking – Done? No Yes Port A =R (Count)[8:15] Hand shaking – Done? No Yes Count ++ Count < 2048 Done No Yes

13 Software  Lab View Chosen as interface program  Main focus on software will be done in next semester.

14 Done so far  Full Hardware definition: Parts was chosen Parts was chosen Voltage & Freq decided Voltage & Freq decided All parts Have been Ordered All parts Have been Ordered Full ORCAD schematic done Full ORCAD schematic done  Detailed Flow charts & protocols defined for each process (Sampling, Write…)

15 Time table  Final design of the board, and delivering it to production.  Chart to HDL compiled + Testing HDL By Leonardo  DIO Ramp up and initial testing.  Writing HDL to ALTERA and start testing  Exams and Vacation  22/6 Till 1/6  From 1/6 Till 6/7  From 6/7 Till 13/7  From 13/7 30/7  8-10/03