9/20/05ELEC 5970-001/6970-001 Lecture 81 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

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9/20/05ELEC / Lecture 81 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Glitch Elimination Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

9/20/05ELEC / Lecture 82 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

9/20/05ELEC / Lecture 83 Power of a Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

9/20/05ELEC / Lecture 84 Dynamic Power Each transition of a gate consumes CV 2 /2. Methods of power saving: –Minimize load capacitances Transistor sizing Library-based gate selection –Reduce transitions Logic design Glitch reduction

9/20/05ELEC / Lecture 85 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards

9/20/05ELEC / Lecture 86 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Output logic state unchanged No transition is necessary

9/20/05ELEC / Lecture 87 Event Propagation Path P1 P2 Path P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

9/20/05ELEC / Lecture 88 Inertial Delay of a Gate d HL d LH d HL +d LH d = ──── 2 V in V out time

9/20/05ELEC / Lecture 89 Given that events occur at the input of a gate with inertial delay d at times, t 1 ≤... ≤ t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t d t n - t 1 t n - t 1 t 1 t 2 t 3 t n t 1 t 2 t 3 t n time time

9/20/05ELEC / Lecture 810 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

9/20/05ELEC / Lecture 811 Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted ?

9/20/05ELEC / Lecture 812 Hazard Filter Method Gate delay is made greater than maximum input path delay difference No delay buffers needed (least transient energy) Overall circuit delay may increase

9/20/05ELEC / Lecture 813 Linear Program Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gate

9/20/05ELEC / Lecture 814 Variables for Full Adder add1b

9/20/05ELEC / Lecture 815 Variables for Full Adder add1b Gate delay variables d 4... d 12 Buffer delay variables d d 29

9/20/05ELEC / Lecture 816 Objective Function Ideal: minimize the number of non-zero delay buffers Actual: sum of buffer delays

9/20/05ELEC / Lecture 817 Specify Critical Path Delay Sum of delays on critical path ≤ maxdel

9/20/05ELEC / Lecture 818 Multi-Input Gate Condition d1 d2 d d1 - d2 ≤ d d2 - d1 ≤ d d d |d1 - d2| ≤ d ≡

9/20/05ELEC / Lecture 819 Results: 1-Bit Adder

9/20/05ELEC / Lecture 820 AMPL Solution: maxdel =

9/20/05ELEC / Lecture 821 AMPL Solution: maxdel =

9/20/05ELEC / Lecture 822 AMPL Solution: maxdel ≥

9/20/05ELEC / Lecture 823 Original 1-Bit Adder Color codes for number of transitions

9/20/05ELEC / Lecture 824 Optimized 1-Bit Adder Color codes for number of transitions

9/20/05ELEC / Lecture 825 Results: 1-Bit Adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

9/20/05ELEC / Lecture 826 References E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp ; also Int. Workshop on Logic Synthesis, May V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp Last two papers are available at website

9/20/05ELEC / Lecture 827 A Limitation Constraints are written by path enumeration. Since number of paths in a circuit can be exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

9/20/05ELEC / Lecture 828 Timing Window Define two timing window variables per gate output: –t i Earliest time of signal transition at gate i. –T i Latest time of signal transition at gate i. t 1, T 1 t n, T n t i, T i Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002 i

9/20/05ELEC / Lecture 829 Linear Program Gate variables d 4... d 12 Buffer Variables d d 29 Corresponding window variables t 4... t 29 and T 4... T 29.

9/20/05ELEC / Lecture 830 Multiple-Input Gate Constraints For Gate 7: T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ;

9/20/05ELEC / Lecture 831 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

9/20/05ELEC / Lecture 832 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

9/20/05ELEC / Lecture 833 Comparison of Constraints Number of gates in circuit Number of constraints

9/20/05ELEC / Lecture 834 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

9/20/05ELEC / Lecture 835 Results: 4-Bit ALU maxdelayBuffers inserted Power Savings : Peak = 33 %, Average = 21 %

9/20/05ELEC / Lecture 836 Power Calculation in Spice VDD Ground Circuit Large C Open at t = 0 Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p t Energy, E(t) E(t) = -- C VDD C V 2 ~ C VDD ( VDD - V ) V

9/20/05ELEC / Lecture 837 Power Dissipation of ALU4 Energy in nanojoules microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

9/20/05ELEC / Lecture 838 F0 Output of ALU4 Signal Amplitude, Volts nanoseconds Original ALU, delay = 7 units (~3.5ns) Minimum energy ALU, delay = 21 units (~10ns) 5 0

9/20/05ELEC / Lecture 839 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) No. of Buffers Average Peak Normalized Power

9/20/05ELEC / Lecture 840 Physical Design Gate l/w Gate l/w Gate l/w Gate l/w Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996). Layout circuit with some nominal gate sizes. Enter extracted routing delays in LP as constants and solve for gate delays. Change gate sizes as determined from a linear system of equations. Iterate if routing delays change.

9/20/05ELEC / Lecture 841 Power Dissipation of ALU4

9/20/05ELEC / Lecture 842 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp T. Raja, A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002.

9/20/05ELEC / Lecture 843 Conclusion Glitch-free design through LP: constraint-set is linear in the size of the circuit. LP solution: –Eliminates glitches at all gate outputs, –Holds I/O delay within specification, and –Combines path-balancing and hazard-filtering to minimize the number of delay buffers. Linear constraint set LP produces results exactly identical to the LP requiring exponential constraint-set. Results show peak power savings up to 68% and average power savings up to 64%.