CPSC 668Set 8: More Mutex with Read/Write Variables1 CPSC 668 Distributed Algorithms and Systems Fall 2009 Prof. Jennifer Welch

CPSC 668Set 8: More Mutex with Read/Write Variables2 Number of R/W Variables Bakery algorithm used 2n shared read/write variables. Tournament tree algorithm used 3n shared read/write variables. Can we do (asymptotically) better, in terms of fewer variables? No!

CPSC 668Set 8: More Mutex with Read/Write Variables3 Lower Bound on Number of Variables Theorem (4.19): Any no-deadlock mutual exclusion algorithm using read/write variables must use at least n shared variables. Proof Strategy: Show by induction on n there must be at least n variables. For each n, there is a configuration in which n variables are covered: means some processor is about to write to it.

CPSC 668Set 8: More Mutex with Read/Write Variables4 Appearing Quiescent Two configurations C and D are P-similar if each processor in P has same state in C as in D and each shared variable has same value in C as in D. A configuration is quiescent if all processors are in remainder section. To make the induction go through, the configuration whose existence we prove must appear quiescent to a set of processors: –C is P-quiescent if there is a quiescent configuration D such that C and D are P-similar

CPSC 668Set 8: More Mutex with Read/Write Variables5 Warm-Up Lemma Before a processor can enter its CS, it must write to an uncovered variable. Lemma (4.17): If C is p i -quiescent, then there is a p i -only schedule  such that (a)p i is in CS in  (C) and (b)during exec(C,  ), p i writes to a variable that is not covered in C.

CPSC 668Set 8: More Mutex with Read/Write Variables6 Proof of Warm-Up Lemma (a) Since C is p i -quiescent, it looks the same to p i as some quiescent D. By ND, some p i -only schedule  exists starting at D in which p i enters CS. When  starts at C, p i also enters CS.  p i in CS by ND D quiescent C p i -quiescent  p i in CS

CPSC 668Set 8: More Mutex with Read/Write Variables7 Proof of Warm-up Lemma (b) Suppose in contradiction when  is executed starting at C, p i writes to the set of variables W but all the variables in W are covered in C. Let P be the set of processors covering the variables in W. 11 CE one step by each proc in P; over- writes W Q 22 successively invoke ND to cause all procs to be in remainder; p i takes no step  some p j (not p i ) takes steps alone; by ND eventually p j enters CS

CPSC 668Set 8: More Mutex with Read/Write Variables8 Proof of Warm-up Lemma (b) 11 CE overwrites W Q 22 successively invoke ND  p j -onlyp j in CS 11 E' overwrites W Q' 22 successively invoke ND  p j -onlyp j in CS, p i in CS Only difference between C and C' are the writes by p i, but those values are overwritten in  1 so the info is lost. C'  p i -only, writes to W p i in CS

CPSC 668Set 8: More Mutex with Read/Write Variables9 Main Result For all k between 1 and n, for all quiescent C, there exists D s.t. (a)D is reachable from C by steps of p 0,…,p k-1 only (b)p 0,…,p k-1 cover k distinct variables in D (c)D is {p k,…,p n-1 }-quiescent. implies desired result when k = n

CPSC 668Set 8: More Mutex with Read/Write Variables10 Proof of Main Result - Basis By induction on k. Basis: k = 1. Must show for all quiescent C, there exists D s.t. (a)D is reachable from C by steps of p 0 only (b)p 0 covers a variable in D (c)D looks quiescent to the other procs. By warm-up lemma (a), if p 0 takes steps alone, it eventually writes to some var. Desired D is just before p 0 's first write.

CPSC 668Set 8: More Mutex with Read/Write Variables11 Proof of Main Result - Induction Assume for k, show for k+1. C C1C1 any qui. config. only p 0 to p k-1 take steps p 0 to p k-1 cover W; p k to p n-1 qui. 00 p k -only  p k covers x not in W  p 0 to p k-1 overwrite W, become quiescent D1'D1' p k in entry looks qui. to rest

CPSC 668Set 8: More Mutex with Read/Write Variables12 Proof of Main Result - Induction C C1C1 any qui. config. only p 0 to p k-1 take steps p 0 to p k-1 cover W; p k to p n-1 qui. 00 p k -only  p k covers x not in W p 0 to p k-1 o'write W, become quiescent D1'D1' p k in entry looks qui. to rest  D1D1 qui. C2C2  p 0 to p k-1 only p 0 to p k-1 cover W; p k to p n-1 qui.  C2'C2'  p 0 to p k cover W and x; p k+1 to p n-1 qui. but why is the same set of k vars covered again?

CPSC 668Set 8: More Mutex with Read/Write Variables13 Proof of Main Result - Fix The result of applying  to D 1 might result in a different set of k variables, W', being covered instead of W. If W' includes x, we have not succeeded in covering an additional variable. To fix this problem, repeatedly apply inductive hypothesis to get C 1,D 1,C 2,D 2,C 3,D 3,… Since number of variables is finite, there exist i and j such that in C i and C j the same set of k variables is covered. Then apply same argument as before, replacing C 1 and C 2 with C i and C j.

CPSC 668Set 8: More Mutex with Read/Write Variables14 Fast Mutual Exclusion The read/write mutex algorithms we've seen so far require a processor to access f(n) variables in the entry section even if no contention. It would be nice to have a fast algorithm: if no competition, a processor enters CS in O(1) steps. Even better would be an adaptive algorithm: performance depends on number of currently competing processors, not total number.

CPSC 668Set 8: More Mutex with Read/Write Variables15 Fast Mutual Exclusion Note that multi-writer shared variables are required to be fast. Combine two mechanisms: –provide fast entry when no contention –provide no deadlock with there is contention

CPSC 668Set 8: More Mutex with Read/Write Variables16 Contention Detector Overview A doorway mechanism captures a set of processors that are concurrently accessing the detector Use a race to choose a unique one of the captured processors to "win"

CPSC 668Set 8: More Mutex with Read/Write Variables17 Contention Detector Uses two shared variables, door and race. Initially door = "open", race = -1. 1race := id 2if door = "closed" then return "lose" 3else 4 door := "closed" 5 if race = id then return "win" 6 else return "lose"

CPSC 668Set 8: More Mutex with Read/Write Variables18 Analysis of Contention Detector Claim: At most one processor wins the contention detector. Why? Let K be set of procs. that read "open" from door in Line 2. Let p j be proc. that writes to race most recently before door is first set to "closed". No node p i other than p j can win: –If p i is not in K, it loses in Line 2. – If p i is in K, it writes race before p j does but checks again (Line 5) after p j 's write and loses.

CPSC 668Set 8: More Mutex with Read/Write Variables19 Analysis of Contention Detector Claim: If p i executes the contention detector alone, then p i wins. Why? Trace through the code when there is no concurrency.

CPSC 668Set 8: More Mutex with Read/Write Variables20 Ensuring No Deadlock If there is concurrency, it is possible that no processor wins the contention detector. To ensure progress: –nodes that lose the contention detector participate in an n-processor ME alg. –The winner of the n-processor alg. competes with the (potential) winner of the contention detector using a 2-processor ME alg. –Winner of 2-processor alg. can enter CS

CPSC 668Set 8: More Mutex with Read/Write Variables21 Ensuring No Deadlock contention detector n-proc. mutex 2-proc. mutex critical section lose win play role of p 0 play role of p 1

CPSC 668Set 8: More Mutex with Read/Write Variables22 Discussion of Fast Mutex Be careful about the exit section: contention detector needs to be reset properly This is a modular presentation: doesn't specify particular n-proc and 2-proc subroutine mutex algorithms Not adaptive: even if only 2 procs are contending, execute the potentially expensive n-proc algorithm