Digital System Clocking:

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Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Presentation transcript:

Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Clock Frequency of Selected Historic Computers and Supercomputers System Intro Date Technology Class Nominal Clock Period (nS) Frequency (MHz) Cray-X-MP Cray-1S,-1M CDC Cyber 180/990 IBM 3090 Amdahl 58 IBM 308X Univac 1100/90 MIPS-X HP-900 Motorola 68020 Bellmac-32A 1982 1980 1985 1986 1981 1984 1987 MSI ECL ECL LSI ECL LSI TTL VLSI CMOS Vector Processor Mainframe Microprocessor Micro-mainframe 9.5 12.5 16.0 18.5 23.0 24.5, 26.0 30.0 50.0 55.6 60.0 125.0 105.3 80.0 62.5 54.1 43.5 40.8,38.5 33.3 20.0 18.0 16.7 8.0 Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

The concept of Finite-State Machine: FSM (Hoffman Model) Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Another Representation of FSM Clocked Storage Elements: Flip-Flops and Latches should be viewed as synchronization elements, not merely as storage elements ! Their main purpose is to synchronize fast and slow paths: prevent the fast path from corrupting the state Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Another Representation of FSM Clocked Storage Elements: Flip-Flops and Latches should be viewed as synchronization elements, not merely as storage elements ! Their main purpose is to synchronize fast and slow paths: prevent the fast path from corrupting the state Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

State Changes in the Finite-State Machine Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Diagram of a Pipelined System Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Machine Execution Phases with Respect to the Clock Cycles Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Increase in the Clock Frequency and Decrease in the Number of Logic Levels Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

System clocking schemes: (a) single-phase clock; (b) two-phase clock; (c) multiple-phase clock

Local generation of Two-Phase Clocks as used in IBM S/390 G4 Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

(a) Crystal oscillator (b) Temperature-compensated crystal oscillator

On-Chip Clock Insertion Delay Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Phase-Locked Loop Block Diagram and Operation Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Delay-Locked Loop Block Diagram and Operation Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

PLL Frequency Multiplication Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Ring-Oscillator-Based VCO with CMOS Inverters as Delay Elements Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

LC Tank-Based VCO, Equivalent AC Circuit Model and Current Waveform Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Clock Parameters: Period (T), Width, Rise and Fall Times Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Clock Parameters: Period, Width, Clock Skew and Clock Jitter Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Clock Uncertainties Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

The Concept of Logic Islands (Wagner 1988), Copyright  1988 IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Clock Tuning Points (Wagner 1988), Copyright  1988 IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Various Clock Shaping Elements and Obtained Clock Signals. (Wagner 1988), Copyright  1988 IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Clock distribution network within a system, (b) on the board, and (c) tuning of the clock. (Wagner 1988), Copyright  1988 IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Clock distribution methods: (a) an RC matched tree, and (b) a grid (Bailey and Benschneider 1998), Copyright  1988, IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic RC delay matched clock distribution topologies: (a) a binary tree, (b) an H tree, (c) an X tree, (d) an arbitrary matched RC matched tree (From Bailey in Chandrakasan et al. 2001), Copyright  1988, IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic

Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic Clock distribution grid used in a DEC Alpha 600-MHz processor (Bailey and Benschneider 1998), Copyright  1988, IEEE Nov. 14, 2003 Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic