Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Lecture 6 - Logic & Arithmetic Fall 2004 Reading: , B.5, B.6 Reminder: Homework Due Monday 9/20: Prob. 2.1, 2.4, 2.6, 2.30, 2.31, 2.34, 2.37, 2.38 Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s Slides - Fall 1999 CMU other sources as noted ORACLE Arithmetic Unit Image Source: Oak Ridge National Laboratory

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic2 Roadmap for the Term: Major Topics  Computer Systems Overview  Technology Trends  Instruction Sets (and Software)  Logic and Arithmetic   Performance  Processor Implementation  Memory Systems  Input/Output

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic3 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic   Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction  Carry Lookahead: Making Addition Fast  ALU Design  Shifters  Summary

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic4 Review: Positional Notation of Numbers  Example: Binary (base 10) numbers  Base = 2  Digits = {0,1} Note “bit” == “Binary digit”  N = 1001 two =  X   +  X   +  X   +  X   = 1 ten + 8 ten = 9 ten  Example: Hexadecimal (base 16) numbers  Base = 16  Digits = {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}  N = 1A3F hex =  X   +  X   +  X   +  X   = 15 ten + 48 ten ten ten = 6719 ten = two

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic5 Range of Unsigned Binary Numbers

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic6 Review: Unsigned vs. Signed Numbers  Basic binary - allows representation of non-negative numbers only In C, Java, etc:unsigned int x; Useful for unsigned quantities like addresses  Most of us need negative numbers, too! In C, Java, etc:int x; How can we do this? … Use a signed representation

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic7 Signed Number Representations  Sign/Magnitude  Two’s Complement - the one almost everyone uses  One’s Complement  Biased - used for exponent sign in Floating Point

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic8 Sign/Magnitude Representation  Approach: Use binary number and added sign bit  Problems:  Two values of zero  Difficult to implement in hardware - consider addition Must first check signs of operands Then compute value Then compute sign of result 1 Sign Magnitude = -25

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic9 Two’s Complement Representation  Goal: make the hardware easy to design  Approach: explicitly represent result of “borrow” in subtract  Borrow results in “leading 1’s”  Weight leftmost “sign bit” with -2 n-1  Use sign bit to represent “last borrow” N = 1111 tc =  X   +  X   +  X   +  X-   = 7 ten + -8 ten = -1 ten N = 1001 tc =  X   +  X   +  X   +  X-   = 1 ten + -8 ten = -7 ten N = 0101 tc =  X   +  X   +  X   +  X-   = 1 ten + 4 ten = 5 ten  All negative numbers have a “1” in the sign bit  Single representation of zero

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic10 Range of Two’s Complement Numbers

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic11 Negating Two’s Complement Numbers  Important shortcut  Invert the individual bits  Add 1  Result: two’s complement representation of negated number!  Examples (with 4 bits): - (0111) = = (1100) = = (1111) = =

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic12 Other Signed Binary Representations  One’s Complement  Use one’s complement (inverted bits) to represent negated numbers +1 = = Invert(0001) = 1110  Problem: two values of zero (0000, 1111)  Biased  Add an bias (offset) to all numbers Most negative number: = -2 n-1 Zero: = 0 Most positive number: = +2 n-1 -1  Used for exponent in IEEE floating point representation (more about this later)

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic13 Sign Extension  To convert a “narrower” signed number to a “wider” one:  Copy the bits of the narrower number into the lower bits  Copy the sign bit from the narrower number into all of the remaining bits of the result  Example: Converting signed 8-bit byte to 32-bit word: Orignal byte: Orignal byte: Result word: Result word:

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic14 Zero-Padding - for unsigned numbers  To convert a “narrower” unsigned number to a “wider” one  Copy the bits of the narrower number into the lower bits  Copy “zeros” into upper bits of wider number Orignal byte: Result word: Orignal byte: Result word: zeros zeros

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic15 Sign Extension in MIPS  Load-byte (lb) instruction  Loads an 8-bit signed number from memory  Performs sign extension before placing in 32-bit register  Load-byte unsigned (lbu)  Loads an 8-bit unsigned number (e.g., ASCII character) from memory  No sign extension - places byte with leading “0’s” in 32-bit register

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic16 Sign Extension in MIPS I-Format Instructions  I-Format Instructions have 16-bit immediate field  MIPS operations are defined on 32-bit registers  Sign extension performed on immediate operands “when it makes sense”  Sign extension used for addi, beq, bne,...  Zero-padding used for andi, ori,...

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic17 Signed & Unsigned Comparisons  MIPS provides two versions of “set less than”  slt - signed comparison - useful when comparing signed numbers  sltu - unsigned comparison - useful when comparing unsigned numbers (e.g. addresses)  Example: suppose $s0= $s1= what do the following instructions do? sltu $t0, $s0, $s1 slt $t1, $s0, $s > 1, so $t0 = 0 -1 < 1, so $t1 = 1

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic18 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic  Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction   Carry Lookahead: Making Addition Fast  ALU Design  Shifters  Summary

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic19 Review: Binary Addition  Key building block: Full Adder AiAi BiBi SiSi CiCi C i+1 AiAi BiBi CiCi SiSi

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic20 Multiple-Bit Adders  String together Full Adders to form a Ripple Adder A1A1 B1B1 S1S1 C1C1 C2C2 A2A2 B2B2 S2S2 C2C2 C3C3 A3A3 B3B3 S3S3 C3C3 C4C4 A0A0 B0B0 S0S0 C0C0 C1C1 0

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic21 A0A0 B0B0 S0S0 C0C0 C1C1 A1A1 B1B1 S1S1 C1C1 C2C2 A2A2 B2B2 S2S2 C2C2 C3C3 A3A3 B3B3 S3S3 C3C3 C4C4 How to Subtract with an Adder  Recall  Definition of subtraction: A-B = A + (-B)  Two’s Complement Negation Shortcut -B = bit_invert(B)+1 1

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic22 Designing an Adder/Subtractor  Recall  Definition of subtraction: A-B = A + (-B)  Two’s Complement Negation Shortcut -B = bit_invert(B)+1 A0A0 B0B0 S0S0 C0C0 C1C1 A1A1 B1B1 S1S1 C1C1 C2C2 A2A2 B2B2 S2S2 C2C2 C3C3 A3A3 B3B3 S3S3 C3C3 C4C4 Control Add/Sub 0 to add 1 to subtract

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic23 Overflow in addition & subtraction  Overflow - occurs when not enough bits are available to represent the result  Example: unsigned 32-bit result ≥ 2 32  Example: signed 32-bit result < or ≥ 2 31  Detecting overflow - look for different signs in operands vs. result: OperationOperand AOperand BResult A + B≥ 0 < 0 A + B< 0 ≥ 0 A - B≥ 0< 0 A - B< 0≥ 0

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic24 What to do when overflow occurs?  In some languages (e.g., C, Java) - nothing (“responsibility left to the programmer”)  In other languages (e.g. Ada, Fortran) - “notify programmer” through runtime exception  How MIPS handles overflow:  add, sub, addi - runtime exception on overflow  addu, subu, addiu - no runtime exception on overflow Note functions otherwise identical to add, sub, addi … including sign extension in addiu!

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic25 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic  Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction  Carry Lookahead: Making Addition Fast   ALU Design  Shifters  Summary

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic26 Delay in Adders  Review: full adder equations  Sum:s i = a i XOR b i XOR c i  Carry:c i+1 = a i *b i + a i *c i + b i *c i  Delay estimate: 32-bit ripple add  Worst case: A 0 or B 0 to C 32 (or S 31 )  Carry delay - each stage: 2 gate delays  Total delay: 64 gate delays - too high! A0A0 B0B0 S0S0 C0C0 C1C1 A1A1 B1B1 S1S1 C1C1 C2C2 A2A2 B2B2 S2S2 C2C2 C3C3 A3A3 B3B3 S3S3 C3C3 C4C4 0

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic27 Speeding up Carry - Carry Lookahead  Key idea: trade off delay, amount of logic used  Benefit: Faster addition  Cost: much more logic  Define two signals for each adder stage:  Generateg i = a i *b i  Propagatep i = a i + b i  Why use these names?  Adder i will always generate a carry if a i, b i both true  Adder i will propagate a carry input if either or both a i, b i true A0A0 B0B0 S0S0 C0C0 C1C1 11 X

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic28 Carry Lookahead (cont’d)  Now rewrite carry output as function of a i,b i,p i,g i  Original eqn: c i+1 = a i *b i + a i *c i + b i *c i  New eqn:c i+1 = g i + p i *c i  "Flatten" carry function in terms of g i, p i c 1 = g 0 + p 0 *c 0 c 2 = g 1 + p 1 *c 1 = g 1 + p 1 *(g 0 + p 0 *g 0 ) = g 1 + p 1 *g 0 + p 1 *p 0 *c 0 c 3 = g 2 + p 2 *g 1 + p 2 *p 1 *g 0 + p 2 *p 1 *p 0 *c 0 c 4 = g 3 + p 3 *g 2 + p 3 *p 2 *g 1 + p 3 *p 2 *p 1 *g 0 + p 3 *p 2 *p 1 *p 0 *c 0  Add carry lookahead logic that computes c 1 -c 4 in terms of p 0 -p 3 and g 0 -g 3

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic29 Using Carry Lookahead  Practical computation for 4-bit adders, but...  Too expensive for 16 bits or 32 bits! a0a0 b0b0 s0s0 c0c0 Carry In g0g0 p0p0 a1a1 b1b1 s1s1 c1c1 g1g1 p1p1 a2a2 b2b2 s2s2 c2c2 g2g2 p2p2 a3a3 b3b3 s3s3 c3c3 g3g3 p3p3 g3g3 p3p3 g0g0 p0p0 c1c1 g1g1 p1p1 c2c2 g2g2 p2p2 c3c3 c4c4 c0c0 Carry Out G0G0 P0P0 Carry Lookahead Unit

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic30 Using Carry Lookahead  Cost a limiting factor  Practical computation for 4-bit adders, but...  Too expensive for 16 bits or 32 bits!  Alternative: Combine 4-bit Carry-Lookahead Adders  Ripple/Lookahead - string together CLAs  Group-Lookahead - add another level of lookahead

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic31 Ripple/Lookahead Adder b 3 -b 0 a 3 -a 0 AB S c0c0 c4c s 3 -s 0 AB S c0c0 c4c AB S c0c0 c4c AB S c0c0 c4c b 7 -b 4 a 7 -a 4 b 11 -b 8 a 11 -a 8 b 15 -b 12 a 15 -a 12 s 7 -s 4 s 11 -s 8 s 15 -s 12 CLA  String together CLA’s  Faster than ripple adder, but…  Still long delays

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic32 Group Carry-Lookahead  Approach: use carry lookahead for 4-bit groups  “Super Propagate” equations: P 0 = p 3 *p 2 *p 1 *p 0 P 1 = p 7 *p 6 *p 5 *p 4 P 2 = p 11 *p 10 *p 9 *p 8 P 3 = p 15 *p 14 *p 13 *p 12  “Super Generate” equations: G 0 = g 3 + (p 3 *g 2 ) + (p 3 *p 2 * g 1 ) + (p 3 *p 2 *p 1 * g 0 ) G 1 = g 7 + (p 7 *g 6 ) + (p 7 *p 6 * g 5 ) + (p 7 *p 6 *p 5 * g 4 ) G 2 = g 11 + (p 11 *g 10 ) + (p 11 *p 10 * g 9 ) + (p 11 *p 10 *p 9 * g 8 ) G 3 = g 15 + (p 15 *g 14 ) + (p 15 *p 14 * g 13 ) + (p 15 *p 14 *p 13 * g 12 )  Combine groups using second level

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic33 Group Carry-Lookahead b 3 -b 0 a 3 -a 0 b 7 -b 4 a 7 -a 4 b 11 -b 8 a 11 -a 8 b 15 -b 12 a 15 -a 12 s 3 -s 0 AB S c0c CLA P G AB S c0c P G AB S c0c P G AB S c0c P G G0G0 P0P0 C1C1 G1G1 P1P1 C2C2 G2G2 P2P2 C3C3 G3G3 P3P3 C4C4 s 7 -s 4 s 11 -s 8 s 15 -s 12 Group Carry Lookahead Unit c 16

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic34 Delay Comparision - 16 Bit Adder  Ripple Adder  2 gate delays per bit  16 bits  Total: 32 gate delays  Group Lookahead Adder  Generating C 4 (c 16 ) - 2 gate delays from P i, G i  Generating P i, G i - 2 gate delays from p i, g i  Generating p i, g i - 1 gate delay from a i, b i  Total: = 5 gate delays

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic35 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic  Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction  Carry Lookahead: Making Addition Fast  ALU Design   Shifters  Summary

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic36 Arithmetic-Logic Units  Combinational logic element that performs multiple functions:  Arithmetic: add, subtract  Logical: AND, OR A B F(A,B) Operation Select ALU

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic37 Constructing an ALU - First Cut  Construct in bit slices, like the ripple adder  Add gates, multiplexer for logic functions, subtract

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic38 ALU Design - Putting it Together  32 bit

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic39 Overflow Detection in ALUs  Overflow occurs when conditions in Fig. 3.3 are met  Problem B.25: equivalent to testing c msb +1 ≠ c msb

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic40 Supporting the MIPS slt Instruction  Want result of 000…001 when A < B  Modify bit slice hardware

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic41 Supporting the MIPS slt Instruction  Add additional multiplexer input, “Less” to slice Bit 31: 0 Bit 1: 0 Bit 0: 1 if A<B Set (MSB only)

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic42 Supporting the MIPS slt Instruction  Feed “Set” to “Less” input of LSB  It’s actually more complicated than this because of overflow - see text

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic43 Supporting the MIPS slt Instruction  Set “less” to “00….01” when result less than zero  Details - see Fig. B.5.10, B.5.11 pp. B-33 - B-34  Use sign bit - “pass around” to LSB of “less”  Complicated by overflow conditions

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic44 Final Result: ALU Function ALU control inputFunction 000AND 001OR 010add 110subtract 111set on less than A B Result ALU Operation ALU Overflow Zero CarryOut

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic45 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic  Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction  Carry Lookahead: Making Addition Fast  ALU Design  Shifters   Summary

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic46 Shifters  1-bit shift could be implemented in ALU  N-bit shift requires shifter circuit  Basic idea: use 2-1 multiplexers S 2 S 1 S 0 A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic47 16-bit Logarithmic Shifter S 0 (0,1) S 1 (0, 2) S 3 (0, 8) S 2 (0, 4) 6-bit shift

ECE 313 Fall 2004Lecture 6 - Logic & Arithmetic48 Outline - Logic & Arithmetic  Review: Numbers & Arithmetic  Positional Number Systems  Signed Number Representation  Review: Addition & Subtraction  Carry Lookahead: Making Addition Fast  ALU Design  Shifters  Summary 