Spring 07, Feb 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)2 Equivalence Checking  Definition: Establishing that two circuits are functionally equivalent.  Applications:  Verify that a design is identical to specification.  Verify that synthesis did not change the function.  Verify that corrections made to a design did not create new errors.

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)3 Compare Two Circuits  Graphs isomorphic?  Boolean functions identical?  Timing behaviors identical? a c b a c b ff

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)4 ATPG Approach (Miter)   Redundancy of a stuck-at-0 fault, checked by ATPG, establishes equivalence of the corresponding output pair.   If the fault is detectable, its tests are used to diagnose the differences. Circuit 1 (Verified design) Circuit 2 (Sythesized or modified design) stuck-at-0

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)5 Difficulties with Miter  ATPG is NP-complete  When circuits are equivalent, proving redundancy of faults is computationally expensive.  When circuits are different, test vectors are quickly found, but diagnosis is difficult.

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)6 A Heuristic Approach  Derive V1, test vectors for all faults in C1.  Derive V2, test vectors for all faults in C2.  If the combined set, V1+V2, produces the same outputs from the two circuits, then they are probably equivalent.  Reference: V. D. Agrawal, “Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation,” Proc. 13 th International Conf. VLSI Design, January 2000, pp

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)7 Example Circuit C1 x1 x2 x3 x4 C1 C1 = x1 x3 x4 + x2 x3 + x2 x x3 x2 x4 x1 Tests

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)8 Example Circuit C2 x1 x2 x3 x4 C2 C2 = x1 x3 x4 + x2 x3 + x2 x x3 x2 x4 x1 Tests

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)9 C1 ≡ C x3 x2 x4 x1 Tests x3 x2 x4 x1 Tests C1 C2

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)10 C2’: Erroneous Implementation of C2 x1 x2 x3 x4 C2’ C2 = x1 x3 x4 + x2 x3 + x2 x x3 x2 x4 x1 Tests C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 minterm deleted

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)11 Incorrect Result: C1 ≡ C2’ C1 = x1 x3 x4 + x2 x3 + x2 x x3 x2 x4 x1 Tests C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 minterm deleted x3 x2 x4 x1 Tests

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)12 Additional Safeguard   Simulate V1+V2 for equivalence:   Output always 0   No single fault on PI’s detected   Still not perfect C1 (Verified design) C2 (Sythesized or modified design) s-a-0 s-a-1 0

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)13 Probabilistic Equivalence  Consider two Boolean functions F and G of the same set of input variables {X1,..., Xn}.  Let f = Prob(F=1), g = Prob(G=1), xi = Prob(Xi=1)  For any arbitrarily given values of xi, if f = g, then F and G are equivalent with probability 1.  References:  J. Jain, J. Bittner, D. S. Fussell and J. A. Abraham, “Probabilistic Verification of Boolean Functions,” Formal Methods in System Design, vol. 1, pp ,  V. D. Agrawal and D. Lee, “Characteristic Polynomial Method for Verification and Test of Combinational Circuits,” Proc. 9 th International Conf. VLSI Design, January 1996, pp

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)14 Simplest Example  F = X1.X2, f = x1 x2  G = X1+X2, g = (1 – x1)(1 – x2) = 1 – x1 – x2 + x1 x2 = 1 – x1 – x2 + x1 x2  Input probabilities, x1 and x2, are randomly taken from {0.0, 1.0}  We make a wrong decision if f = g, i.e., x1x2 = 1 – x1 – x2 + x1 x2 orx1 + x2 = 1

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)15 Probability of Wrong Decision x1 x2 0 Randomly selected point (x1,x2) x1 + x2 = Probability of wrong decision = Random point falls on line {x1 + x2 = 1} = (area of line)/(area of unit square) = 0

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)16 Calculation of Signal Probability  Exact calculation  Exponential complexity.  Affected by roundoff errors.  Alternative: Monte Carlo method  Randomly select input probabilities  Generate random input vectors  Simulate circuits F and G  If outputs have a mismatch, circuits are not equivalent.  Else, stop after “sufficiently” large number of vectors (open problem).

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)17 References on Signal Probability  S. C. Seth and V. D. Agrawal, “A New Model for Computation of Probabilistic Testability in Combinational Circuits,” INTEGRATION, The VLSI Journal, vol. 7, pp ,  V. D. Agrawal and D. Lee and H. Woźniakowski, “Numerical Computation of Characteristic Polynomials of Boolean Functions and its Applications,” Numerical Algorithms, vol. 17, pp , 1998.

Spring 07, Feb 8ELEC 7770: Advanced VLSI Design (Agrawal)18 More on Equivalence Checking  Don’t cares  Sequential circuits  Time-frame expansion  Initial state  Design debugging (diagnosis)  Reference: S.-Y. Hwang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging, Springer, 1998.