Lab 6 Program Counter and Program ROM Mano & Kime Sections 7-1 – 7-6.

Slides:

Advertisements

Similar presentations

WHYP Test Files Lab 9. y1 The WC16 WHYP Core Modifications for Multiplication and Division.

Advertisements

Arbitrary Waveform Discussion 5.5 Example 34.

7-Segment Display: Spartan-3 board

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Top-level VHDL Designs

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Multiplication Discussion Multiplier Binary Multiplication 4 x 4 Multiplier.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

A Simple Microcontroller VHDL Tutorial R. E. Haskell and D. M. Hanna T6: VHDL State Machines.

Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3.

Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM.

Multi-Base Calculator CSE378 Final Project By Matthew Lehn & Yanqing Zhu December 17, 2001 Professor Haskell.

Structural VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T3: ALU Design.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Multiplication Discussion Multiplier Binary Multiplication 4 x 4 Multiplier.

Lecture L6.2 VHDL Multiply Operator (*)

Lab 2 4-Bit Adder Digilent Spartan 3 Board Lecture L2.3.

The FC16 Forth Core Lab 7 Module F4.1. Lab 7 Hex OpcodeNameFunction 0000NOP No operation 0001DUP Duplicate T and push data stack. N

Digilab 7-Segment Displays Lab 4. selyInstruction name “000”true if b = a false otherwise = “001”true if b /= a false otherwise “010”true if b < a.

Sequencing and Control Mano and Kime Sections 8-1 – 8-7.

Finite State Machines Discussion D8.1 Example 36.

Logic Design Fundamentals - 2 Lecture L1.2. Logic Design Fundamentals - 2 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

7-Segment Displays Digilent Spartan 3 Board Discussion DS-4.2.

A Programming Language for the FC16 Forth Core

Introduction to VHDL Multiplexers Discussion D1.1.

Programming Example Lecture 8.6 A VHDL Forth Core for FPGAs: Sect. 7.

7-Segment Displays VHDL Tutorial R. E. Haskell and D. M. Hanna T4: Xilinx LogiBLOX.

Registers Lab 5 Mano and Kime Sections 5-2, 5-3, 5-7.

Sequential Multiplication Lecture L6.4. Multiplication 13 x = 8Fh 1101 x

LCD Display DIO2 Board CPLD. DIO2 Board CPLD Interface LCD Display.

RS-232 Port Lecture L9.3. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)

Data Stack Instructions Lab 7. Data Stack WHYP Data Stack Instructions DUP( n -- n n ) SWAP( a b -- b a ) DROP( a -- ) OVER( a b -- a b a ) ROT( a.

4-Bit Binary-to-BCD Converter: case Statement

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

Other WC16 Instructions Lecture L7.4. OpcodeNameFunctionNumber of Clock Cycles Fetch the byte at address T in RAM and load it into T1 Fetch.

VHDL Examples Subra Ganesan Reference: Professor Haskell’s Notes,

4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.

1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.

VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f

EE3A1 Computer Hardware and Digital Design Lecture 5 Testbenches and Memories in VHDL.

Main Project : Simple Processor Mini-Project : 3-bit binary counter (using 7400 series) Memory By Oluwayomi B. Adamo.

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

15-Dec-15EE5141 Chapter 4 Sequential Statements ä Variable assignment statement ä Signal assignment statement ä If statement ä Case statement ä Loop statement.

Digital System Projects

 Seattle Pacific University EE Logic System DesignCounters-1 Shift Registers DQ clk DQ DQ ShiftIn Q3Q3 Q2Q2 DQ Q1Q1 Q0Q0 A shift register shifts.

1 Part III: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

Lecture 8 Review Combinational Devices –Decoder –Multiplexor (Bhasker p-81) –Shifter –Barrel Shifter (Bhasker p-303)

George Mason University Behavioral Modeling of Sequential-Circuit Building Blocks ECE 545 Lecture 8.

Lecture 11 Xilinx FPGA Memories Part 2

Prime Numbers Lecture L6.1 Sieve of Eratosthenes.

Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.

Main Project : Simple Processor Mini-Project : Vending Machine Memory

ENG6530 Reconfigurable Computing Systems

Fast, Asynchronous SRAM

Mano and Kime Sections 7-6 – 7-8

مدار های ترکیبی دیکدر لامپ های هفت قسمتی یکی از دیکدر هایی که اغلب به کار برده می شود،دیکدر 4 به 7 برای تبدیل کد bcd به کد هفت بیتی برای لامپ های seven.

A Data Stack CoreGen Discussion 12.1.

A Greatest Common Divisor (GCD) Processor

Fibonacci Sequence Lecture L4.1 Lab 3.

Multiplication Discussion 11.1.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Data Flow Description of Combinational-Circuit Building Blocks

DIO2 Board Projects.

Fast, Asynchronous SRAM

High-Low Guessing Game

Return Stack Lab 8.

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

Presentation transcript:

Lab 6 Program Counter and Program ROM Mano & Kime Sections 7-1 – 7-6

Program Counter

Program Counter, PC library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC is port ( d: in STD_LOGIC_VECTOR (15 downto 0); clr: in STD_LOGIC; clk: in STD_LOGIC; inc: in STD_LOGIC; pload: in STD_LOGIC; q: out STD_LOGIC_VECTOR (15 downto 0) ); end PC;

architecture PC_arch of PC is signal COUNT: STD_LOGIC_VECTOR (15 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= " "; elsif clk'event and clk='1' then if pload = '0' then if inc = '1' then COUNT <= COUNT + 1; end if; else COUNT <= d; end if; q <= COUNT; end process; end PC_arch;

Program ROM

package opcodes is subtype opcode is std_logic_vector(15 downto 0); -- Register instructions --WHYP WORDS constant nop: opcode := X"0000";-- NOP constant dup: opcode := X"0001";-- DUP constant swap: opcode := X"0002"; -- SWAP -- Function unit instructions constant plus: opcode := X"0010"; -- + constant minus: opcode := X"0011"; -- - constant plus1: opcode := X"0012"; constant minus1: opcode := X"0013"; constant invert: opcode := X"0014"; -- INVERT constant andd: opcode := X"0015"; -- AND constant orr: opcode := X"0016"; -- OR constant xorr: opcode := X"0017"; -- XOR constant twotimes: opcode := X"0018"; -- 2* constant u2slash: opcode := X"0019"; -- U2/ constant twoslash: opcode := X"001A"; -- 2/ constant rshift: opcode := X"001B"; -- RSHIFT constant lshift: opcode := X"001C";-- LSHIFT constant ones: opcode := X"0020";-- TRUE constant zeros: opcode := X"0021";-- FALSE

constant zeroequal: opcode := X"0022";-- 0= constant zeroless: opcode := X"0023";-- 0< constant ugt: opcode := X"0024"; -- U> constant ult: opcode := X"0025"; -- U< constant eq: opcode := X"0026"; -- = constant ugte: opcode := X"0027";-- U>= constant ulte: opcode := X"0028";-- U<= constant neq: opcode := X"0029"; -- <> constant gt: opcode := X"002A"; -- > constant lt: opcode := X"002B"; -- < constant gte: opcode := X"002C";-- >= constant lte: opcode := X"002D";-- <= -- I/O instructions constant sfetch: opcode := X"0037"; -- constant digstore: opcode := X"0038"; -- DIG! -- Transfer instructions constant lit: opcode := X"0100"; -- LIT constant jmp: opcode := X"0101"; -- AGAIN, ELSE constant jz: opcode := X"0102"; -- IF, UNTIL constant jb4HI: opcode := X"010D"; -- waitB4 constant jb4LO: opcode := X"0109"; end opcodes;

\ WHYP program to multiply switch settings by 10 HEX : MAIN ( -- ) BEGIN waitBTN4\ wait to push BTN4 3Bn DIG!\ 3Bn waitBTN4\ 3B wait to push BTN4 2*\ 762n DUP\ n 2n 2*\ 76 EC2n 4n 2*\ 76 1D82n 8n +\ 24E10n DIG!\ 24E AGAIN ;

waitBTN4 Compilation of waitBTN JB4HI, X"0000",-- X"00" wait for BTN4 up 0002 JB4LO, X"0002",-- X"02" wait for BTN4 Note: BTN4 is ‘0’ or LO when not pressed BTN4 is ‘1’ or HI when pressed

Program ROM, Prom6 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.opcodes.all; entity Prom6 is port ( addr: in STD_LOGIC_VECTOR (15 downto 0); M: out STD_LOGIC_VECTOR (15 downto 0) ); end Prom6;

architecture Prom6_arch of Prom6 is subtype tword is std_logic_vector(15 downto 0); type rom_array is array (0 to 18) of tword; constant rom: rom_array := ( JB4HI, X"0000",-- X"00" wait for BTN4 up JB4LO, X"0002",-- X"02" wait for BTN4 SFETCH,-- X"04" push switches digstore,-- X"05" display JB4HI, X"0006",-- X"06" wait for BTN4 up JB4LO, X"0008",-- X"08" wait for BTN4 twotimes,-- X"0A" 2* DUP,-- X"0B" DUP twotimes,-- X"0C" 2* twotimes,-- X"0D" 2* plus,-- X"0E" + digstore,-- X"0F" display JMP, X"0000",-- X"10" GOTO 0 X"0000"-- X"12" );

begin process(addr) variable j: integer; begin j := conv_integer(addr); M <= rom(j); end process; end Prom6_arch;

Digit Display

dig7seg.vhd

digdisplay.vhd dig7seg