Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Sequential Logic Flip Flops Registers Memory Timing State Machines.

Slides:

Advertisements

Similar presentations

Chapter 5 Internal Memory

Advertisements

Programmable Logic PAL, PLA.

Computer Science 210 Computer Organization Clocks and Memory Elements.

1 Fundamentals of Computer Science Sequential Circuits.

CPS3340 COMPUTER ARCHITECTURE Fall Semester, /23/2013 Lecture 7: Computer Clock & Memory Elements Instructor: Ashraf Yaseen DEPARTMENT OF MATH &

Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.

Module 12.  In Module 9, 10, 11, you have been introduced to examples of combinational logic circuits whereby the outputs are entirely dependent on the.

Chapter 3 Digital Logic Structures. 3-2 Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000):

Sequential circuit Digital electronics is classified into combinational logic and sequential logic. In combinational circuit outpus depends only on present.

EECC341 - Shaaban #1 Lec # 13 Winter Sequential Logic Circuits Unlike combinational logic circuits, the output of sequential logic circuits.

Chapter 10. Memory, CPLDs, and FPGAs

Allocating Space for Variables Global data section –All global variables stored here (actually all static variables) –R4 points to beginning Run-time stack.

Overview Finite State Machines - Sequential circuits with inputs and outputs State Diagrams - An abstraction tool to visualize and analyze sequential circuits.

Overview Logic Combinational Logic Sequential Logic Storage Devices SR Flip-Flops D Flip Flops JK Flip Flops Registers Addressing Computer Memory.

Overview Recall Combinational Logic Sequential Logic Storage Devices

Registers  Flip-flops are available in a variety of configurations. A simple one with two independent D flip-flops with clear and preset signals is illustrated.

Chapter 5 Internal Memory

Seqeuential Logic State Machines Memory

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Transistor: Building.

COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.

Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Timing Sequential Logic Flip Flops Registers Memory State Machines.

Midterm Wednesday Chapter 1-3: Number /character representation and conversion Number arithmetic CMOS logic elements Combinational logic elements and design.

Sequential circuits part 2: implementation, analysis & design All illustrations  , Jones & Bartlett Publishers LLC, (

Flip Flops. Clock Signal Sequential logic circuits have memory Output is a function of input and present state Sequential circuits are synchronized by.

Registers and Counters

Test #2 Combinational Circuits – MUX Sequential Circuits – Latches – Flip-flops – Clocked Sequential Circuits – Registers/Shift Register – Counters – Memory.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Building Functions.

Introduction to Digital Logic Design Appendix A of CO&A Dr. Farag

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Basic Logic Gates.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Combinational vs.

Flip-Flops and Registers

Digital Logic Design Instructor: Kasım Sinan YILDIRIM

SEQUENTIAL CIRCUITS Component Design and Use. Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data 

Introduction to Computer Engineering ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin.

1 Lecture 22 Sequential Circuits Analysis. 2 Combinational vs. Sequential  Combinational Logic Circuit  Output is a function only of the present inputs.

 Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences.

Asynchronous vs. Synchronous Counters Ripple Counters Deceptively attractive alternative to synchronous design style State transitions are not sharp! Can.

1 Memory Design EE 208 – Logic Design Chapter 7 Sohaib Majzoub.

Chapter 3 Digital Logic Structures. 3-2 Combinational vs. Sequential Combinational Circuit always gives the same output for a given set of inputs  ex:

SEQUENTIAL LOGIC By Tom Fitch. Types of Circuits Combinational: Gates Combinational: Gates Sequential: Flip-Flops Sequential: Flip-Flops.

Chapter 3 Digital Logic Structures

PART 3 Digital Logic 1.Logic Gates 2.Logic Circuits 3.Memory 4.Sequential Circuits 5.LC-3 Data Path.

Computer Architecture and Organization Unit -1. Digital Logic Circuits – Logic Gates – Boolean Algebra – Map Simplification – Combinational Circuits –

Introduction to Computer Engineering CS/ECE 252, Spring 2012 Prof. Karu Sankaralingam Computer Sciences Department University of Wisconsin – Madison.

Introduction to Computer Engineering CS/ECE 252, Fall 2007 Prof. David A. Wood Computer Sciences Department University of Wisconsin – Madison.

Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain.

1 Lecture #11 EGR 277 – Digital Logic Ch. 5 - Synchronous Sequential Logic There are two primary classifications of logic circuits: 1.Combinational logic.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Transistor: Building.

Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.

CO5023 Latches, Flip-Flops and Decoders. Sequential Circuit What does this do? The OUTPUT of a sequential circuit is determined by the current output.

Introduction to Computing Systems and Programming Digital Logic Structures.

Synchronous Sequential Circuits by Dr. Amin Danial Asham.

Latches, Flip Flops, and Memory ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin – Madison.

Dept. of Electrical Engineering

Digital Logic Structures. Transistor: The Digital Building Block Microprocessors contain LOTS of transistors –Intel Pentium 4 (2000): 48 million –IBM.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Transistor: Building.

Sequential Logic Circuit Design Eng.Maha Alqubali.

Appendix C Basics of Logic Design. Appendix C — Logic Basic — 2 Logic Design Basics §4.2 Logic Design Conventions Objective: To understand how to build.

Computer Science 210 Computer Organization

Computer Architecture & Operations I

Class Exercise 1B.

Morgan Kaufmann Publishers

FIGURE 5.1 Block diagram of sequential circuit

Basics of digital systems

Computer Science 210 Computer Organization

Chapter 11 Sequential Circuits.

Computer Science 210 Computer Organization

Chapter 3 Digital Logic Structures

Sequential Logic.

CMPE212 Discussion 11/21/2014 Patrick Sykes

Presentation transcript:

Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Sequential Logic Flip Flops Registers Memory Timing State Machines

Lab Breadboard Strips 4 Sets of connected pin holes run horizontally on the top and bottom of the strip (good for running/connecting power and ground) Approximately 60 sets of connected pin holes run vertically in the middle of the strip (good for connecting power to pins and connections between pins) Note: Use Bell wire to make connections. You might want to color code wires by function.

Logical Completeness Can implement ANY truth table with AND, OR, NOT. 1. AND combinations that yield a "1" in the truth table. 2. OR the results of the AND gates. ALSO: Can implement ANY truth table with ONLY NANDS. Can implement ANY truth table with ONLY NORS.

Programmmable Logic Arrays (PLAs)

Major Types of Flip Flops Non- Clocked S R Clocked (Edge Triggered, LevelTriggered, Master/Slave) D J/K Note: D and J/K FlipFlops often have S & R inputs also

D Flip Flop (D Latch) D | Qn+1 0 | 0 1 | 1

JK Flip Flop J K | Qn | Q n 0 1 | | | not Q n

JK as a Universal Flip Flop JK as an SR – use set and pre inputs JK as a Toggle – connect J and K JK as a D – connect NOT J to K

Register A register stores a multi-bit (vector) value. –We use a collection of D-latches, all controlled by a common write enable pulse, call it WE. –When the write enable WE=1, the n-bit value D is written to register.

2 2 x 3 Memory address decoder word selectword WE address write enable input bits output bits

2 2 x 3 Memory – 1 Decoder, 3 Multiplexors

2 2 x 3 Memory – Read of Word at Address 11

Memory Design – 1K x 4 A[09:00]   D[03:00] Addr Block Select 

Memory Design – 1K x 8 A[09:00]    D[07:04] A[09:00]    D[03:00] Addr Block Select => D[07:04] D[03:00]

Memory Design - 2k x 8 D[07:04] D[03:00] Block 01 Block 00

Memory Design - 4k x 8 D[07:04] D[03:00] Block 11 Block 10 Block 01 Block 00

1K X 4 SRAM (Part Number 2114N)

More Memory Details Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM) –fast, maintains data as long as power applied Dynamic RAM (DRAM) –slower but denser, bit storage decays – must be periodically refreshed. Refreshing interferes with regularity of execution of instruction stream. Also, non-volatile memories: ROM, PROM, flash, …

Alternative Logic “Family” Choices Totempole: High or Low output level (Most Common) Line always at a 1 level or 0 level Tristate: High, Low, or Open (Good for BUS application) Like Totempole, but has third state – open state Open Collector, Open Drain, Wired-OR: (Older alternative to Tristate – still used, but more susceptible to noise) Line is nominally at a 1 level or 0 level – line is “pulled” to non-nominal level. Outputs of and gates can be connected directed together to create an “OR condition. Differential: (Used for driving signals a distance. Good noise immunity) Uses a pair of lines – the “level” is the difference of signals on the two lines.

Timing Diagram Conventions

Synchronous Timing Diagram

Asynchronous Timing – Read Diagram

Asynchronous Timing – Write Diagram

Combinational vs. Sequential Circuits Combinational Circuit –always gives the same output for a given set of inputs example: adder always generates sum and carry, regardless of previous inputs Sequential Circuit –has memory - “stores” information, –output depends on stored information (state) plus input so a given input might produce different outputs, depending on the stored information –example: ticket counter advances when you push the button output depends on previous state –useful for building “memory” elements and “state machines”