High Current Density and High Power Density Operation of Ultra High Speed InP DHBTs Mattias Dahlström 1, Zach Griffith, Young-Min Kim 2, Mark J.W. Rodwell Department of ECE University of California, Santa Barbara, USA , fax (1) Now with IBM Microelectronics, Essex Junction, VT (2) Now with Sandia National Labs, NM

Overview Fast devices and circuits need high current! –Current limited by Kirk current threshold Device heating –Thermal resistance  Device heating Design of low thermal resistance HBT High Current Devices with state of the art RF performance

The need for high current density Scaling laws: Single HBT: f  J e =6.9 mA/  m 2 Output GHz, f clk = GHz Minimize capacitance charging times!  Increase current density Digital circuit Key performance parameters: J e =8 mA/  m 2

Thermal conductivity of common materials Ternaries lattice matched to InP

HBT: Where is the heat generated? V be = 0.95 V, V ce = 1.3 V Power generation: J E x V CE =6 x 1.5 V=9 mW/  m 2 In the intrinsic collector

HBT: heat transport Main heat transport is through the subcollector to the substrate Up to 30 % heat transport up through the emitter contact Thermal resistance of materials in collector and subcollector critical

How to design a low thermal resistance HBT A five step process Identify high thermal resistance materials  change them low thermal resistance materials Very simple!

SHBT: InGaAs collector Design of low thermal resistance HBT: Initial design: InGaAs collector

SHBT: InGaAs collector, InP emitter Design of low thermal resistance HBT: Emitter: InAlAs  InP

DHBT: InGaAs/InP collector Design of low thermal resistance HBT: InGaAs collector  InP collector with InGaAlAs grade

DHBT: InGaAs/InP collector, InGaAs/InP subcollector Design of low thermal resistance HBT: InGaAs subcollector  InGaAs/InP composite subcollector

DHBT: InGaAs/InP collector, thin InGaAs/InP subcollector Design of low thermal resistance HBT: Thick InGaAs in subcollector  thin InGaAs in subcollector

Metamorphic-DHBT: InGaAs/InP collector, InGaAs/InP subcollector Design of low thermal resistance Metamorphic HBT: InAlAs,InAlP, InGaAs buffers  InP buffer Young-Min Kim

Experimental Measurement of Temperature Rise Temperature rise can be calculated by measuring I C, V CE and  V BE No thermal instability as long as slope<∞ each V BE gives a unique I C

Thermoelectric feedback coefficient (data from W. Liu) Thermoelectric feedback coefficient for AlGaAs/GaAs HBTs 4 % smaller Not a large influence from material or structure variations W. Liu: “Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 42 No6, June 1995 W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities of InP-Based Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 43 No3, March 1996

Compared to previous UCSB mesa HBT results: Thinner InP collector—decrease  c Collector doping increased—increase J Kirk Thinner InGaAs in subcollector—remove heat Thicker InP subcollector—decrease R c,sheet High f  DHBT Layer Structure and Band Diagram V be = 0.75 V, V ce = 1.3 V Emitter Collector Base InGaAs 3E19 Si 400 Å InP 3E19 Si 800 Å InP 8E17 Si 100 Å InP 3E17 Si 300 Å InGaAs 8E19  5E19 C 300 Å Setback 3E16 Si 200 Å InP 3E18 Si 30 Å InP 3E16 Si 1030 Å SI-InP substrate Grade 3E16 Si 240 Å InP 1.5E19 Si 500 Å InGaAs 2E19 Si 125 Å InP 3E19 Si 3000 Å

Thermal resistance results: lattice matched Measured thermal resistances for lattice matched HBTs. Ic= 5 mA, Vce=1.5 V, P=7.5 mW 25 nm InGaAs 12.5 nm InGaAs DeviceBuffer (  m) T c (nm)T sc InGaAs (nm) T sc InP (nm)  ­ JA K/mW DHBT-M DHBT-19b DHBT nm InGaAs  25 nm InGaAs: large improvement

Thermal resistance results: metamorphic Measured thermal resistances for metamorphic HBTs. Ic= 5 mA, Vce=1.5 V, P=7.5 mW 25 nm InGaAs InP buffer 50 nm InGaAs InAlP buffer InAlP  InP buffer: large improvement 50 nm InGaAs  25 nm InGaAs: small improvement Device Buffer (  m) T c (nm)T sc InGaAs (nm) T sc InP (nm)  ­ JA K/mW M-HBT-1InAlP M-HBT-2InP M-HBT-11InP

Device and circuit results Zach Griffith Continuous operation at high current densities greater than peak rf performance (J e = 8 mA/  m 2 ) 28 transistor static frequency f clk =118.7 GHz shown To be reported, 150 GHz static divider using same Type 1 DHBT structure—chirped superlattice Transistor operation at 13 mA/  m nm InGaAs/InP collector 370 GHz f t at J c >8 mA/  m 2

Our Mesa DHBTs have Safe Operating Area Extending beyond High-Speed Logic Bias Conditions Low-current breakdown is > 6 Volts this has little bearing on circuit design Safe operating area is > 10 mW/um 2 these HBTs can be biased....at ECL voltages...while carrying the high current densities needed for high speed

Conclusions DHBT design with InP subcollector  very low thermal resistance Metamorphic DHBT with InP buffer  low thermal resistance DHBT operation at J c >13 mA/  m 2 Optimal device and circuit performance at J c up to 8 mA/  m 2 HBT I-V operating area allows static frequency dividers operating at speeds over 150 GHz

Backup slides

HBT

Why is thermal management important? As J increases so does the power density. This will lead to an increase in the temperature. TCTC J Kirk LeLe ÅmAμm -2 μm For V CE =1V  P D =10.6mWμm -3 For V CE =1V  P D =98mWμm -3 !!

Thermal Modeling of HBT (1) 3D Finite Element using Ansys 5.7 K (Thermal conductivity) depends temperature K depends on doping For GaAs heavily doped GaAs 65% less than undoped GaAs Unknown for InP or InGaAs use GaAs dependency J.C.Brice in “Properties of Indium phosphide” eds S Adachi and J.Brice pubs INSPEC London p20-21 S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p34-39 “CRC Materials science and engineering handbook”, 2nd edition,eds J.F Shackelford,A.Alexander, and J.S Park, pubs CRC press, Boca Raton, p270 MaterialK 300 nK 300 (exp)Refs InP InGaAs Au  Large uncertainty in values

Validation of Model Caused by Low K of InGaAs Max T in Collector Ave Tj (Base-Emitter) =26.20°C Measured Tj=26°C Good agreement. Advice Limit InGaAs Increase size of emitter arm Ian Harrison

Analysis of 40,80,160 Gbit/s devices To obtain speed inprovements require to scale other device parameters. Speed(Gbit/s) Collector Thickness(Å) Base Sheet resistance ()() Base contact resistance (-m2)(-m2) Base Thickness(Å) Base Mesa width (  m) Current Density (mA/  m 2 ) Emitter. Junction Width (  m) Emitter Parasitic resistivity (-m2)(-m2) Emitter Length (  m) Predicted MS-DFF(GHz) FtFt (GHz) F max (GHz) TjTj (K) T Max (K) T Max (No Etch Stop layer)(K) Conservative 1.5x bit rate Reduction of parasitic C BC Device parameters after Rodwell et al When not switching values will double Ian Harrison

Mesa DHBT with 0.6  m emitter width, 0.5  m base contact width Z. Griffith, M Dahlström

How we measure thermal resistance

Layout improvement: Emitter heat sinking Emitter interconnect metal  2 μm to 7 μm ~30 % of heat out through emitter Negligible increase in C be Improved emitter heatsinking