17th TM on Research Using Small Fusion Devices Real-Time Digital Systems for Control on Small Tokamaks Presented by: Bernardo B. Carvalho Association Euratom/IST on behalf of the CFN Data Acquisition Group and ISTTTOK Team

17th TM on Research Using Small Fusion Devices Introduction:Traditional Architectures Small tokamaks usually rely on pre-programmed waveforms for open-loop control of plasma parameters Tokamak: Sensor (Magnetics) Sensor (Interferometry) Waveform Generator #1 Actuator (Power Suplies) Actuator (Gas Puffing) Waveform Generator #2 DATA ACQUISITION SYSTEM “Trial-and-error” type operation Hard to get similar discharges, as the plasma is a multivariable complex system Reprogram of waveforms is normally an empiric and lengthy task Data acquired needs to be correlated manually against control waveforms

17th TM on Research Using Small Fusion Devices Plasma Control Plasma close-loop control on medium/small tokamaks example: Tokamak Sensor (Magnetics) Actuator (PSU) Sensor (Pressure/ Interferometry) Single-Input Single-Output (SISO) ANALOG controllers Not easily Re-configurable Hard to Optimize Allows only simple control schemes (e.g PID) Control of Plasma Parameters is NOT coupled! Actuator (Gas Puffing) Controller #1 (PID) Controller #2 (PID) Sensor X Actuator Y Controller # (PID)

17th TM on Research Using Small Fusion Devices Recent digital technologies and tools developed at IST enable a New Paradigm Integrated Digital Control System, Sensors-to- Actuator, based on available low-cost technologies General Purpose Processors: Intel, PowerPC… Open-Source Standards and Real-Time Operating Systems: XML, CORBA, SQL, RTAI DSP - Digital Signal Processors FPGA- Field Programmable Gate Arrays MIMO Multiple Input- Multiple Output Controller Dedicated real-time synchronous network for event and timing distribution

17th TM on Research Using Small Fusion Devices Application: The ISTTOK Plasma Control PCI-TR-512 Acq. & Control Module 8 Diff. bit/ 2 Msamples /sec Galvanic Isolated. 512 Mbytes of SDRAM Synchronization of clock and trigger among boards (Master-Slave) Integrated FPGA and DSP for data processing Digital output for Control Purposes See Poster 26 ISTTOK Plasma Control System 12 Magnetic Probes on a poloidal circular section Fast position determination code running on DSP (128 μs) using 8 signals Two PWM controlled PSU for Vertical and Horizontal Equilibrium Fields Data transmitted to PSU by optical connection

17th TM on Research Using Small Fusion Devices Next Step: Upgrade of ISTTOK Plasma Control Present ISTTOK Tomography Diagnostic: Three pinhole camera Each camera with 10 active channels Two different reconstruction methods Fourier-Bessel Algorithm (Faster ~40 μs) Neural-Network (~400 μs) Reconstruction algorithms running and tested on a standard PC with RTAI OS See Poster P13 Goal: Multi-Diagnostic Plasma Control System Magnetic reconstruction using 12 probes(+), Vloop and Rogoswky coil Tomography reconstruction used when magnetic reconstruction fails to give reliable results ( e.g. during current inversion in AC operation) HFS LFS

17th TM on Research Using Small Fusion Devices New system overview

17th TM on Research Using Small Fusion Devices ATCA-Based System Why ATCA? Reliable mechanics (serviceability, shock and vibration) High security and regulatory conformances Highly configurable Robust power infrastructure and large cooling capacity (200W per board) Ease of integration of multiple functions and new features Supports 14 slots in 19” cabinet or smaller versions Ability to host multiple controllers and storage on a shelf

17th TM on Research Using Small Fusion Devices ATCA Backplane Topologies Advanced ATCA Interface Topologies DUAL-STAR BACKPLANE FULL MESH BACKPLANE Multi-protocol support for interfaces up to 20 Gb/s Each slot is interconnected through up to four 2.5 Gb/s links with an actual throughput capacity of ~800 MByte/s per link Scalable aggregated shelf capacity to 2.5Tb/s

17th TM on Research Using Small Fusion Devices Low-Cost ATCA Controller-Processor Module Based on a PC plain ATX Motherboard with PCIe, assembled on a specially designed ATCA Carrier Board Any Processor in the ix86 multi-core family Easily upgraded to higher processing power Processing power over 40 GFLOPS and a set of SIMD instructions Plain Linux or Real-time OS (RTAI) Connected to the PCI Express™ switch fabric of the ATCA™ carrier by an ×16 full-duplex link (8 GB/s) directly from its Northbridge Occupies 2 slots of the ATCA shelf

17th TM on Research Using Small Fusion Devices ATCA 32-Channel Digitizer Module 32 Analogue differential Inputs ±32V dynamic range, 18-bit resolution Anti-aliasing filters and Galvanic isolation Simultaneous sampling at 2 MHz programmable Decimation down to 1 kHz on the FPGA Optional I/O Rear Transition Module: 8 analogue 16-bit/50MSPS 8 digital input/output channels (EIA-485) 1 fiber optic port (x1 full-duplex 500 MB/s) SFP RS-232 interface Developed for JET Vertical Stabilization Enhancement Project EP2 Digitizer Main board Digitizer Carrier board ATCABUSATCABUS Optional RTM I/O ATCA MODULE

17th TM on Research Using Small Fusion Devices ATCA FAST Data Acquisition Module ATCA Digitizer Module 8 channel with up to 250 High Power FPGA Multi-rate filtering based on events Local Control algorithms Can Implement PHA and data reduction in real-time Developed for JET Gamma Ray Spectroscopy Enhancement Project EP2

17th TM on Research Using Small Fusion Devices Digital Link for the Actuators TP3 - Hard real-time communications protocol for Trigger, Timing and data Transport (Developed under JET Vertical Stabilization Enhancement EP2 Project) OGSL - Optical gigabit serial link Transmits the control signals to the actuator units, enough to attain low loop delays (< 1us). Developed for JET Vertical Stabilization Enhancement Project Fiber optic SFP LC-Duplex connector (850 nm over 62.5/125 μm fiber) Full-duplex communications with programmable signaling rate from 622 Mbaud to Gbaud EHSL - Electrical high-speed serial link 2/4 wire RS-485 (ANSI TIA/EIA-485-A) Up to 8 half-duplex or 4 full-duplex channels on a 37 pin D-sub connector Programmable signaling rate up to 30 Mbaud

17th TM on Research Using Small Fusion Devices Firmware Tools Hardware Level –FPGA: Data Reduction, Pulse Processing, Timing, Event Detection and Distribution VHDL, Verilog, (in future directly SCILAB, MATLAB, etc) –DSP: Fast plasma position determination and PID control algorithms C, Assembly –dsPIC: PWM control of PSU Assembly Example 1: Block Diagram of real time sampling decimation Example 2: Block Diagram of real time PHA Implementation in FPGA for Gamma Ray Spectroscopy

17th TM on Research Using Small Fusion Devices Software Tools Local Processor Node –RTOS: Real time multi-diagnostic reconstruction and control algorithms RTAI, C / C++ –FIRESIGNAL “Node”: Data storage, parameter programming and integration in the general control and acquisition system (FIRESIGNAL SERVER) C++ Code/ CORBA Event Based Configuration data described in XML format Standardized hardware description

17th TM on Research Using Small Fusion Devices Summary  Small tokamaks are adequate platforms to develop Control and Data Acquisition Systems using State-of-Art digital technologies and tools (PCIe, ATCA, RTAI, XML)  IST/CFN’s future work will build on previous developments towards ITER relevant solutions  New machines (or enhancements of the existent) represent crucial opportunities to explore new concepts compatible with ITER requirements with benefits to the ITER CODAC Specification  Common remote collaboration tools and unified data description methods will boost collaboration between Labs