1 of 14 1/15 Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems Paul Pop, Petru Eles, Zebo Peng Embedded Systems Lab (ESLAB) Linköping University, Sweden

2 of 14 2/15... Factory Systems Heterogeneous Networks Distributed Heterogeneous System... Heterogeneous Networks Multi-Cluster Systems... NoCs Automotive Electronics...

3 of 14 3/15 Distributed Safety-Critical Applications... Unsolved problems Gateway  Applications distributed over heterogeneous networks are difficult to...  Analyze (e.g., guaranteeing timing constraints)  Design (e.g., efficient implementation)  Applications distributed over the heterogeneous networks  Reduce costs: use resources efficiently  Requirements: close to sensors/actuators

4 of 14 4/15  Design optimization  Several design problems can be addressed once an analysis is available. Contributions  Analysis and design of Multi-Cluster Embedded Systems  Analysis  Proposed a schedulability analysis for safety-critical hard real-time applications mapped on multi-cluster distributed embedded systems  Is the application schedulable? (Are deadlines satisfied?)  Bounds on the communication delays and communication buffer sizes  Design optimization  In this paper we have addressed communication synthesis and priority assignment for  Improving the degree of schedulability of an application  Minimizing communication buffer sizes needed to run a schedulable application

5 of 14 5/15 Outline  Motivation  Contributions  System architecture and application model  Schedulability analysis for multi-clusters  Optimization strategies  Experimental results  Message and future work

6 of 14 6/15 S0S0 S1S1 S2S2 SGSG S0S0 S1S1 S2S2 SGSG TDMA Round Cycle of two rounds Slot Time Triggered Protocol (TTP)  Bus access scheme: time-division multiple-access (TDMA)  Schedule table located in each TTP controller: message descriptor list (MEDL) Controller Area Network (CAN)  Priority bus, collision avoidance  Highest priority message wins the contention  Priorities encoded in the frame identifier Hardware Architecture Gateway... Time-triggered cluster  Static cyclic scheduling  Time-triggered protocol Event-triggered cluster  Fixed priority preemptive scheduling  Controller area network protocol

7 of 14 7/15 CPU NGNG Out CAN TTP Controller S1S1 SGSG Round2 P4P4 P1P1 CPU N1N1 TTP Controller MBI CPU MBI CAN Controller CPU N2N2 CAN Controller T m1m1 m2m2 m1m1 S1S1 SGSG Out TTP T P2P2 P3P3 Out N2 m3m3 m3m3 Software Architecture... Time-triggered cluster Event-triggered cluster Gateway

8 of 14 8/15 Problem Formulation  Input  An application modeled as a set of process graphs  Each process has an worst case execution time, a period, and a deadline  Each message has a known size  The system architecture and the mapping of the application are given Application: set of process graphs... Architecture: Multi-clusterMapping  Output  Worst case response times and bounds on the buffer sizes  Design implementation such that the application is schedulable and buffer sizes are minimized  Schedule table for TT processes  Priorities for ET processes  Schedule table for TT messages  Priorities for ET messages  TT bus configuration (TDMA slot sequence and sizes) Communication infrastructure parameters System configuration parameters

9 of 14 9/15  Scheduling event-triggered activities:  Response time analysis: calculate worst case response times for each process  Schedulability test: response times smaller than the deadlines Schedulability Analysis  Scheduling time-triggered activities:  Building a schedule table: static cyclic scheduling (e.g., list scheduling)  Communication delays  Bounds on the buffer sizes  Response times depend on the communication delay between sending and receiving a message  Communication delays depend on the type of message passing 1.TTC  TTC 2.TTC  ETC 3.ETC  ETC 4.ETC  TTC

10 of 14 10/15 Multi-Cluster Scheduling  Scheduling cannot be addressed separately for each type of cluster  The inter-cluster communication creates a circular dependency:  TTC static schedules (offsets)  ETC response times  ETC response times  TTC schedule table construction Application, Mapping, Architecture TT Bus Configuration Priorities Schedule Tables Response times Static Scheduling Multi-Cluster Scheduling Offsets Response Times Offset earliest possible start time for an event-triggered activity Bounds on the buffer sizes Response Time Analysis

11 of 14 11/15 Optimization Example TTP CAN N1N1 NGNG N2N2 P2P2 P3P3 O3O3 O2O2 m1m1 m3m3 m2m2 SGSG S1S1 SGSG P1P1 S1S1 SGSG P4P4 Deadline missed! TTP CAN N1N1 NGNG N2N2 O3O3 O2O2 m1m1 m3m3 m2m2 S1S1 SGSG SGSG S1S1 SGSG P1P1 P4P4 P2P2 P3P3 Deadline met Transformation: S 1 is the first slot, m 1 and m 2 are sent sooner N1N1 NGNG N2N2 O3O3 O2O2 m1m1 m3m3 m2m2 SGSG S1S1 SGSG S1S1 P1P1 P2P2 P3P3 P4P4 TTP CAN Deadline met Transformation: P 2 is the high priority process on N 2...

12 of 14 12/15 Optimization Strategies  OptimizeSchedule  Synthesizes the communication and assigns priorities to obtain a schedulable application  Based on a greedy approach  Cost function: degree of schedulability  OptimizeBuffers  Synthesizes the communication and assigns priorities to reduce the total buffer size  Based on a hill-climbing heuristic  Cost function: total buffer size  Straightforward solution  Finds a schedulable application  Does not consider the optimization of the design

13 of 14 13/15 Can We Improve Schedulability? Average Percentage Deviation [%] Number of processes 120 Simulated Annealing Near-optimal values for the degree of schedulability Straightforward solution Does not perform optimizations Cost function: degree of schedulability OptimizeSchedule? OptimizeSchedule

14 of 14 14/15 Can We Reduce Buffer Sizes? 0 2k 4k 6k 8k 10k Average total buffer size [k] Number of processes Simulated Annealing Near-optimal values for the total buffer size OptimizeSchedule Does not optimize the total buffer size Cost function: total buffer size OptimizeBuffers? OptimizeBuffers  Case study  Vehicle cruise controller  Distributed over the TT and ET clusters

15 of 14 15/15 Message and Future Work  Future Work  Explore more design problems  Mapping for multi-clusters  How to partition an application in ET and TT activities? Analysis and optimization methods are needed for the efficient implementation of applications distributed over interconnected heterogeneous networks.