1 Portable Heart Attack Detector (PHAD) Mid Semester Presentation May 25, 2005 Technion – Israel Institute of Technology Department of Electrical Engineering High-Speed Digital Systems LabSupervisor Daniel Alkalay System architectures Nir Gluzman Alexei Iolin

2 AGENDA Project objective System block diagram Project status Implementation problems Next steps

3 Develop a system that measures and displays RR-rate, ST-elevation and alert to wide-QRS. Implement the system on National-Instrument (*) Real-Time FPGA development environment using LabView graphical language. Project objective (*) (*) website: PXI-7831R

4 Basic ECG complex R P Q S T

5 System block diagram Biosensors A/D interface Detection of ECG characteristic points with DWT (Discrete Wavelet Transform) Detection of RR-rate, ST-elevation, wide-QRS Abnormalities alert

6 Project status Study of NI/FPGA & LabView development environment 3 Implementation 5 Design verification 2 Limited clinical experiments (optional) 1 Final report and project summary 2 Subject Time period (weeks)

7 Implementation problems ECG characteristic points are detected with DWT (Discrete Wavelet Transform). DWT block Source: A wavelet-based ECG delineator: evaluation on standard databases, IEEE Transaction on biomedical engineering, April 2004.

8 Two filter-bank implementation for DWT: Mallat’s algorithm (original design). “Algorithme à trous” (implementation without decimation). Implementation problems DWT block (cont.)

9 Lab experience with NI/FPGA implementation for FIR filters and decimators is limited (because it’s a new system). Decimators implementation with current version of NI/FPGA modules is complicated. Decision block adjustment is needed if we re-design DWT block (Mallat  algorithme à trous). Implementation problems DWT block (cont.)

10 Block is based on running RMS calculations for ‘R’ detection. Implementation problems Decision block R-trigger block

11 Current version of NI/FPGA doesn’t include an RMS module. Running RMS can be implemented in software (“host”). Host disadvantage - RMS parallel calculations cannot be implemented. Implementation problems Decision block (cont.)

12 NI/FPGA calculations are done in fix point. DWT block is based on FIR filters  loss of filter stability isn’t expected. System performance degradation due to the use of fix-point is expected to be low. Implementation problems Floating point VS. fix point

13 Re-design of DWT block (Mallat  algorithme à trous) and decision block. Consulting with NI Israeli representative regarding improved DSP modules for FPGA: Meeting is scheduled to List of questions were ed to NI representative abroad. Due to time constraints we put our effort on system re-designing for NI/FPGA current capabilities. Next steps

14 Questions?