May 17, 2001Mixed-Signal Test and DFT: Mixed-Signal Test and DFT Vishwani D. Agrawal Agere Systems, Murray Hill, NJ May 17, 2001

Mixed-Signal Test and DFT: VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

May 17, 2001Mixed-Signal Test and DFT: Costs of Testing n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

May 17, 2001Mixed-Signal Test and DFT: Cost of Manufacturing Testing in 2000AD n GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

May 17, 2001Mixed-Signal Test and DFT: Testing Principle

May 17, 2001Mixed-Signal Test and DFT: Characterization Test n Worst-case test Choose test that passes/fails chips Select statistically significant sample of chips Repeat test for every combination of 2+ environmental variables Plot results in Schmoo plot Diagnose and correct design errors n Continue throughout production life of chips to improve design and process to increase yield

May 17, 2001Mixed-Signal Test and DFT: Manufacturing Test n Determines whether manufactured chip meets specs n Must cover high % of modeled faults n Must minimize test time (to control cost) n No fault diagnosis n Tests every device on chip n Test at speed of application or speed guaranteed by supplier

May 17, 2001Mixed-Signal Test and DFT: Burn-in or Stress Test n Process: Subject chips to high temperature & over- voltage supply, while running production tests n Catches: Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers Freak failures – devices having same failure mechanisms as reliable devices

May 17, 2001Mixed-Signal Test and DFT: Test Specifications & Plan n Test Specifications: Functional Characteristics Type of Device Under Test (DUT) Physical Constraints – Package, pin numbers, etc. Environmental Characteristics – supply, temperature, humidity, etc. Reliability – acceptance quality level (defects/million), failure rate, etc. n Test plan generated from specifications Type of test equipment to use Types of tests Fault coverage requirement

May 17, 2001Mixed-Signal Test and DFT: Automatic Test Equipment Components n Consists of: Powerful computer Powerful 32-bit Digital Signal Processor (DSP) for analog testing Test Program (written in high-level language) running on the computer Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad)

May 17, 2001Mixed-Signal Test and DFT: ADVANTEST Model T6682 ATE

May 17, 2001Mixed-Signal Test and DFT: LTX FUSION HF ATE

May 17, 2001Mixed-Signal Test and DFT: Test Process Summarized n Parametric tests – determine whether pin electronics system meets digital logic voltage, current, and delay time specs n Functional tests – determine whether internal logic/analog sub-systems behave correctly n ATE Cost Problems Pin inductance (expensive probing) Multi-GHz frequencies High pin count (1024) n ATE Cost Reduction Multi-Site Testing DFT methods like Built-In Self-Test

May 17, 2001Mixed-Signal Test and DFT: Mixed-Signal Testing Problem

May 17, 2001Mixed-Signal Test and DFT: Differences from Digital Testing n Size not a problem – at most 100 components n Much harder analog device modeling No widely-accepted analog fault model Infinite signal range Tolerances depend on process and measurement error Tester (ATE) introduces measurement error Digital / analog substrate coupling noise Absolute component tolerances +/- 20%, relative +/- 0.1% n Multiple analog fault model mandatory No unique signal flow direction

May 17, 2001Mixed-Signal Test and DFT: Present-Day Analog Testing Methods n Specification-based (functional) tests Main method for analog – tractable and does not need an analog fault model Intractable for digital -- # tests is huge n Structural ATPG – used for digital, just beginning to be used for analog (exists) n Separate test for functionality and timing not possible in analog circuit Possible in digital circuit

May 17, 2001Mixed-Signal Test and DFT: DSP Tester Concept

May 17, 2001Mixed-Signal Test and DFT: Waveform Synthesis Needs sin x / x (sinc) correction – Finite sample width

May 17, 2001Mixed-Signal Test and DFT: Waveform Sampling Sampling rate > 100 ks/s

May 17, 2001Mixed-Signal Test and DFT: A/D and D/A Test Parameters n A/D -- Uncertain map from input domain voltages into digital value (not so in D/A) Two converters are NOT inverses n Transmission parameters affect multi-tone tests Gain, signal-to-distortion ratio, intermodulation distortion, noise power ratio, differential phase shift, envelop delay distortion n Intrinsic parameters – Converter specifications Full scale range (FSR), gain, # bits, static linearity (differential and integral), maximum clock rate, code format, settling time (D/A), glitch area (D/A)

May 17, 2001Mixed-Signal Test and DFT: Ideal Transfer Functions A/D ConverterD/A Converter

May 17, 2001Mixed-Signal Test and DFT: Offset Error

May 17, 2001Mixed-Signal Test and DFT: Gain Error

May 17, 2001Mixed-Signal Test and DFT: D/A Transfer Function Non-Linearity Error

May 17, 2001Mixed-Signal Test and DFT: Differential Linearity Error n Differential linearity function – How each code step differs from ideal or average step (by code number), as fraction of LSB n Subtract average count for each code tally, express that in units of LSBs n Repeat test waveform 100 to 150 times, use slow triangle wave to increase resolution

May 17, 2001Mixed-Signal Test and DFT: Linear Histogram and DLE of 8-bit ADC

May 17, 2001Mixed-Signal Test and DFT: DSP-Based Testing n DSP-based tester has: Waveform Generator Waveform Digitizer High frequency clock with dividers for synchronization n A/D and D/A Test Parameters Transmission Intrinsic n A/D and D/A Faults: offset, gain, non-linearity errors Measured by DLE, ILE, DNL, and INL n A/D Test Histograms – static linear and sinusoidal n D/A Test –- Differential Test Fixture

May 17, 2001Mixed-Signal Test and DFT: DSP-Based Test Concepts n Quantization Error – Introduced into measured signal by discrete sampling n Quantum Voltage – Corresponds to flip of LSB of converter n Single-Tone Test -- Test of DUT using only one sinusoidal tone Tone – Pure sinusoid of f, A, and phase  n Transmission (Performance) Parameter -- indicates how channel with embedded analog circuit affects multi-tone test signal  UTP – Unit test period: joint sampling period for analog stimulus and response

May 17, 2001Mixed-Signal Test and DFT: Spectral Test of A/D Converter

May 17, 2001Mixed-Signal Test and DFT: Spectral Components in DSP-Based Testing

May 17, 2001Mixed-Signal Test and DFT: A/D Converter Spectrum Audio source at 1076 Hz sampled at 44.1 kHz

May 17, 2001Mixed-Signal Test and DFT: Coherent Multi-Tone Testing

May 17, 2001Mixed-Signal Test and DFT: Analog Test Bus n PROs: Usable with digital JTAG boundary scan Adds analog testability – both controllability and observability Eliminates large area needed for analog test points n CONs: May have a 5 % measurement error C-switch sampling devices couple all probe points capacitively, even with test bus off – requires more elaborate (larger) switches Stringent limit on how far data can move through the bus before it must be digitized to retain accuracy

May 17, 2001Mixed-Signal Test and DFT: Analog Test Bus Diagram

May 17, 2001Mixed-Signal Test and DFT: Analog Boundary Module

May 17, 2001Mixed-Signal Test and DFT: Chaining of ICs

May 17, 2001Mixed-Signal Test and DFT: Partitioning for Test n Partition according to test methodology: Logic blocks Memory blocks Analog blocks n Provide test access: Boundary scan Analog test bus n Provide test-wrappers (also called collars) for cores.

May 17, 2001Mixed-Signal Test and DFT: Test-Wrapper for a Core n Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. n Test-wrapper provides: For each core input terminal n A normal mode – Core terminal driven by host chip n An external test mode – Wrapper element observes core input terminal for interconnect test n An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core For each core output terminal n A normal mode – Host chip driven by core terminal n An external test mode – Host chip is driven by wrapper element for interconnect test n An internal test mode – Wrapper element observes core outputs for core test

May 17, 2001Mixed-Signal Test and DFT: A Test-Wrapper Wrapper test controlle r Scan chain to/from TAP from/to External Test pins Wrapper elements Core Functional core inputs Functional core outputs

May 17, 2001Mixed-Signal Test and DFT: Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K G  where 1 < K < 5, and  ~ 0.5. Assume that block area A is proportional to G, i.e., t is proportional to A 0.5. Since test logic is added to each terminal t, Test logic added to terminals Overhead = ~ A –0.5 A

May 17, 2001Mixed-Signal Test and DFT: DFT Architecture for SOC User defined test access mechanism (TAM) Module 1 Test wrapper Test source Test sink Module N Test wrapper Test access port (TAP) Functional inputs Functional outputs Func. inputs Func. outputs SOC inputs SOC outputs TDI TCK TMS TRST TDO Instruction register control Serial instruction data

May 17, 2001Mixed-Signal Test and DFT: DFT Components n Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. n Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. n Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. n Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.

May 17, 2001Mixed-Signal Test and DFT: Summary n Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. n Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. n SOC design for testability: n Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. n Provide external or built-in tests for blocks. n Provide test access via boundary scan and/or analog test bus. n Develop interconnect tests and system functional tests. n Develop diagnostic procedures.