Finite State Machines Discussion D7.1 Mealy and Moore Machines.

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Presentation transcript:

Finite State Machines Discussion D7.1 Mealy and Moore Machines

Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output

Mealy Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2

Moore Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2

VHDL Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output process(clk, init) process(present_state, x)

VHDL Mealy Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2 process(clk, init) process(present_state, x)

VHDL Moore Machine State Register C1 x(t) s(t+1) s(t) z(t) clk init present state present input next state C2 process(present_state, x) process(present_state) process(clk, init)

Example Detect input sequence 1101 fsm din dout clk clr din dout

Use State Diagram Detect input sequence 1101 S0 0 S1 0 S11 0 S110 0 S CLR

fsm.vhd fsm din dout clk clr

fsm.vhd clr dout din

fsm.vhd clr dout din

fsm.vhd S0 0 S1 0 S11 0 S110 0 S CLR

fsm.vhd S0 0 S1 0 S11 0 S110 0 S CLR

fsm.vhd clr dout din

fsmx.vhd fsm clk_pulse BTN(3) BTN(1) LD(0) LD(7) din dout clr clk fsmx clkdiv mclk cclk BTN(0) bn LD(1)

fsmx.vhd entity fsmx is port( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN : in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); AtoG : out STD_LOGIC_VECTOR(6 downto 0); dp : out STD_LOGIC; AN : out STD_LOGIC_VECTOR(3 downto 0) ); end fsmx;

fsmx.vhd

component clock_pulse port( inp : in std_logic; cclk : in std_logic; clr : in std_logic; outp : out std_logic); end component; signal clr, clk, cclk, bn: std_logic; signal clkdiv: std_logic_vector(23 downto 0);

fsmx.vhd bn <= BTN(1) or BTN(0); clr <= BTN(3); U0: clk_pulse port map (inp => bn, cclk => cclk, clr =>clr, clk => clk); U1: fsm port map (clr =>clr, clk => clk, din => BTN(1), dout => LD(7)); LD(0) <= BTN(0); LD(1) <= BTN(1);

Detect input sequence 1101