Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis April 4, 2005 MILESTONE 11 LVS & Simulation DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (Done) Gate Level Design (Done) Testing of Top-Level Schematic (Done) LVS of Entire Chip (98%) LVS of FP Adder (Done) LVS of FP Multiplier (Done) LVS of Delay for Comb (Done) Simulations (50%) To Be Done Connect Few Remaining Bus Lines at Top Level Top Level Simulation Optimizations – Add Buffers & Reduce White Space

DESIGN DECISIONS Modified Registers to Improve Testing Added Reset Vertically Stretched FP Adder Reduces need to use Metal4 to allow room for global routing along left side

STRATEGY for TESTING & CRITICAL PATH ESTIMATION Strategy for Testing Test the main components individually Floating Point Adder Floating Point Multiplier Comb Test the top level Simpler to more complex inputs Critical Path Currently determining, but believe it’s a particular path through the FP_Adder

LAYOUT – Delay (Comb)

LAYOUT – FP LVS version /02/ :45 (intelibm5) $ Like matching is enabled. Using terminal names as correspondence points. Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/layout/netlist count 949nets 39terminals 1111pmos 1111nmos Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/schematic/netlist count 960nets 39terminals 11cds_thru 1111pmos 1111nmos Terminal correspondence points 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13B … The net-lists match. …. It LVS’d!

LAYOUT – FP LVS version /02/ :45 (intelibm5) $ Like matching is enabled. Using terminal names as correspondence points. Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/layout/netlist count 1068nets 37terminals 1232pmos 1232nmos Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha/cds/LVS/schematic/netlist count 1130nets 39terminals 62cds_thru 1232pmos 1232nmos Terminal correspondence points 1FP_1 2FP_1 3FP_1 4FP_1 5FP_1 6FP_1 7FP_1 8FP_1 9FP_1 10FP_1 11FP_1 12FP_1 13FP_2 … The net-lists match. … It LVS’d!

FLOORPLAN – Last Week

TOP LEVEL LAYOUT - Current

SIZE ESTIMATES Transistor Count: 33,654 Area: 423x429 µm (181,467 µm 2 ) Density: ~0.185 Aspect Ratio: ~1:1

VERIFICATION – Top Level Verified all of the functions for the ‘Swiss Army Knife’ in Schematic. Plotted outputs using custom made code & MatLab. From plots it is evident that the accuracy is excellent.

SIMULATIONS – FP Adder ExtractedRC: Rise Time / Fall Time: ~ 1.5ns

SIMULATIONS – FP Mult ExtractedRC: Rise Time / Fall Time: ~ 1.5ns / 500ps

PROBLEMS & QUESTIONS Buffering – Need to Reduce Rise/Fall Times Need to Reduce White Space Improve Density Verified Design & Applications of Both Circuits (w/ & w/o Complex Numbers - Soft IP) w/ DSP TA