Design-Manufacturing Interface Formulations and Algorithms Andrew B. Kahng, CSE 291 Spring

Subwavelength Gap since.35  m Subwavelength Optical Lithography l EUV, X-rays, E-beams all > 10 years out l huge investment in > 30 years of optical litho infrastructure l knobs: direction, phase, aperture, pattern context

Clear areas Opaque (chrome) areas Mask Types l Bright Field –opaque features –transparent background l Dark Field –transparent features –opaque background

Phase Shifting Masks conventional mask glass Chrome phase shifting mask Phase shifter 0 E at mask 0 0 E at wafer 0 0 I at wafer 0

Impact of PSM l PSM enables smaller transistor gate lengths L eff –“critical” polysilicon features only (gate L eff ) –faster device switching  faster circuits –better critical dimension (CD) control  improved parametric yield –all features on polysilicon layer, local interconnect layers –smaller die area  more $/wafer (“full-chip PSM” == BIG win) l Alternative: build a $10B fab with equipment that won’t exist for 5+ years l Data points –exponential increase in price of CAD technology for PSM –25 nm gates (!!!) manufactured with 248nm DUV steppers (NTI + MIT Lincoln Labs, announced June 2000); 90nm gates in production at Motorola, Lucent (since late 1999)

Double-Exposure Bright-Field PSM =

The Phase Assignment Problem l Assign 0, 180 phase regions such that critical features with width (separation) < B are induced by adjacent phase regions with opposite phases Bright Field (Dark Field)

Key: Global 2-Colorability ? If there is an odd cycle of “phase implications”  layout cannot be manufactured –layout verification becomes a global, not local, issue

F4 F2 F3 F1 Critical features: F1,F2,F3,F4

F4 F2 F3 F1 Opposite- Phase Shifters (0,180)

F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7S8 Shifters: S1-S8 PROPER Phase Assignment: –Opposite phases for opposite shifters –Same phase for overlapping shifters

F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7S8 Phase Conflict Proper Phase Assignment is IMPOSSIBLE

F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7S8 Phase Conflict feature shifting to remove overlap Phase Conflict Resolution

F4 F2 F1 S1 S2 S3S4 S7S8 Phase Conflict feature widening to turn conflict into non-conflict Phase Conflict Resolution F3

How will VLSI CAD deal with PSM ? l UCLA: first comprehensive methodology for PSM-aware layout design l Approach: partition responsibility for phase- assignability –Type 1 : good layout practices (local geometry) –(open) problem: is there a set of “design rules” that guarantees phase-assignability of layout ? (no T’s, no doglegs, even fingers...) –Type 2 : automatic phase conflict resolution / bipartization (global colorability) –Type 3 : enabling reuse of layout (free composability) –problem: how can we guarantee reusability of phase-assigned layouts, such that no odd cycles can occur when the layouts are composed together in a larger layout ?

Type 1 Rules: Local Geometry Rules

Local Geometry Rules l Features classified as critical or noncritical –according to dimension and inter-layer interactions –e.g., poly geometry critical if width less than 180nm, OR if width less than 220nm but over active region l Spacing rules depend on feature criticality –e.g., minimum spacing between parallel critical is different from minimum spacing between parallel noncritical l Particular feature shapes can be prohibited –“no critical-width T's” rule is required –“no critical-width doglegs” rule is discretionary

Local Geometry Rules: Example Cases

Type 2 Rules: Automatic Conflict Resolution

Compaction-Oriented Approach l Analyze input layout l Find min-cost set of perturbations needed to eliminate all “odd cycles” l Induce constraints for output layout –i.e., PSM-induced (shape, spacing) constraints l Compact to get phase-assignable layout l Key: Minimize the set of new constraints, i.e., break all odd cycles in conflict graph by deleting a minimum number of edges.

Conflict Graph l Dark Field: build graph over feature regions –edge between two features whose separation is < B l Bright Field: build graph over shifter regions –shifters for features whose width is < B –two edge types –adjacency edge between overlapping phase regions : endpoints must have same phase –conflict edge between shifters on opposite side of critical feature: endpoints must have opposite phase

conflict graph G green = feature; pink = conflict Bright Field: conflict edge adjacency edge conflict graph G Conflict Graph G Dark Field:

Optimal Odd Cycle Elimination conflict graph G dual graph D T-join of odd-degree nodes in D dark green = feature; pink = conflict

Optimal Odd Cycle Elimination corresponds to broken edges in original conflict graph - assign phases: dark green and purple - remaining pink conflicts correctly handled T-join of odd-degree nodes in D dark green = feature; pink = conflict

The T-join Problem l How to delete minimum-cost set of edges from conflict graph G to eliminate odd cycles? l Construct geometric dual graph D = dual(G) l Find odd-degree vertices T in D l Solve the T-join problem in D: –find min-weight edge set J in D such that –all T-vertices have odd degree –all other vertices have even degree l Solution J corresponds to desired min-cost edge set in conflict graph G

Solving T-join in Sparse Graphs l Reduction to matching –construct a complete graph T(G) –vertices = T-vertices –edge costs = shortest-path cost –find minimum-cost perfect matching l Typical example = sparse (not always planar) graph –note that conflict graphs are sparse –#vertices = 1,000,000 –#edges  5  #vertices –# T-vertices  10% of #vertices = 100,000 l Drawback: finding APSP too slow, memory-consuming –#vertices = 100,000  #edges in T(G) = 5,000,000,000

Solving T-join: Reduction to Matching l Desirable properties of reduction to matching: –exact (i.e., optimal) –not much memory (say, 2-3X more) –leads to very fast solution l Solution: gadgets! –replace each edge/vertex with gadgets s.t. matching all vertices in gadgeted graph  T-join in original graph

T-join Problem: Reduction to Matching l replace each vertex with a chain of triangles l one more edge for T-vertices l in graph D: m = #edges, n = #vertices, t = #T l in gadgeted graph: 4m-2n-t vertices, 7m-5n-t edges l cost of red edges = original dual edge costs cost of (black) edges in triangles = 0 vertex  T vertex  T

Example of Gadgeted Graph Dual Graph Gadgeted graph black + red edges == min-cost perfect matching

Results Runtimes in CPU seconds on Sun Ultra-10 Greedy = breadth-first-search bicoloring GW = Goemans/Williamson95 heuristic Cook/Rohe98 for perfect matching Integration w/compactor: saves 9+% layout area vs. GW

F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7S8 Can distinguish between use of shifting, widening DOFs

Black points - features Blue - shifter overlap Red - extra nodes to distinguish opposite shifters Bipartization Problem: delete min # of nodes (or edges) to make graph bipartite - blue nodes: shifting - red nodes: widening Bipartization by node deletion is NP-hard (GW98: 9/4-approx)

Recap l New fast, optimal algorithms for edge-deletion bipartization –Fast T-join using gadgets –applicable to any AltPSM phase conflict graphs l Approximate solution for node-deletion bipartization –Goemans-Williamson98 9/4-approximation –If node-deletion cost < 1.5 edge deletion, GW is better than edge deletion l UCLA code at IBM Burlington, NTI,...

Type 3 Rules: Standard-Cell Composability for P&R Flows

Conflict Graph for Cell-Based Layouts l Coarse view: at level of connected components of conflict graphs within each cell master –each component independently phase-assignable (2 k versions) –treated as a single “vertex” in coarse-grain conflict graph edge in coarse-grain conflict graph cell master Acell master B connected component

Guidelines l PSM must be “transparent” to auto-P&R –“free composability” is the cornerstone of the cell-based methodology! –focus on poly layer  we are concerned with placer, not router –polygon layout information currently not in placement vocabulary –available abstractions: pin EEQs/LEQs, overlap layer geometries l Competitive context for placer –extremely competitive runtime regimes –nontrivial cost of checking placement phase-assignability is unacceptable l Iteration between placer and separate tool is unacceptable l P&R tool MUST deliver guaranteed phase-assignable poly layer

Types of Composability l Same-row composability –any cell can be placed immediately adjacent (in the same row) to any other cell l Adj-row composability –any cell can be placed in an adjacent cell row to any other cell, with the two cells having intersecting x-spans l Four cases of cell libraries (G = guaranteed; NG = not guaranteed) –Case 1: adj-G, same-G –most-constrained cell layout; most transparent to placer –Case 2: adj-G, same-NG –Case 3: adj-NG, same-G –Case 4: adj-NG, same-NG –least-constrained cell layout; least transparent to placer

Case 2: Adj-G, Same-NG Blue vertices, edges = graph of phase assignment “dependencies”

Case 3: Adj-NG, Same-G Blue vertices, edges = graph of phase assignment “dependencies”

Case 1: Adj-G, Same-G l Solution 1: “no restrictions on the cell layout” – create cell abstractions such that placer runs in “normal” mode –e.g., pre-bloat (by 1 site) cells that have critical poly near left/right boundary –e.g., create overlap layer obstacles corresponding to critical poly near top/bottom boundary l Solution 2: smart rules to restrict cell layout –e.g., every pair of boundary-CP features from the same cell must be non-interfering –definition: two features are non-interfering if they are in different connected components of the cell’s phase conflict graph –no boundary-CP feature is “near” two different sides of its cell –these two restrictions  composability guaranteed (no odd cycles possible) l Solution 3: dumb rules to restrict cell layout –all cells have 250nm-wide 0-phase boundary (IBM style)

Cases 2,4: Same-NG l Each (sub)row checked separately, post-placement l Basic tool: cell compatibility table –library is precharacterized by M 2 two-dimensional arrays A ij, one array for each possible pairing of cells with C i to the left of C j –A ij = minimum site separation at which C ip can be placed adjacent to C jq (p = 1, …, V i and q = 1, …, V j ) –example: M = 500 with 16 versions of each master cell  < 30 MB storage l Goals: –(1) if phase assignment possible, return set of versions for each of the cell instances –(2) if not possible, return set of versions plus set of inserted feedthroughs (extra sites) such that minimum perturbation is achieved

Conclusions l Broad PSM effects: DSM P&R, Custom IC, PV, … l Three-part comprehensive EDA methodology for BF- PSM l Partitions responsibility for phase-assignability among three “rule” types –layout creation, automatic conflict resolution, and composability l Support for key subflows –interactive full-custom, automated full-custom, automatic cell- based P&R, layout migration

Density Control for CMP l Chemical-mechanical polishing (CMP) –applied to interlayer dielectrics (ILD) and inlaid metals –polishing pad wear, slurry composition, pad elasticity make this a very difficult process step l Cause of CMP variability –pad deforms over metal feature –greater ILD thickness over dense regions of layout –“dishing” in sparse regions of layout –huge part of chip variability budget used up (e.g., 4000Å ILD variation across-die)

Min-Variation Objective l Relationship between oxide thickness and local feature density l Minimizing variation in window density over layout preferable to satisfying lower and upper density bounds density oxide thickness filling min min’ max

Density Control for CMP l Layout density control –density rules minimize yield impact –uniform density achieved by post-processing, insertion of dummy features l Performance verification (PV) flow implications –accurate estimation of filling is needed in PD, PV tools (else broken performance analysis flow) –filling geometries affect capacitance extraction by > 50% –is a multilayer problem (coupling to critical nets, contacting restrictions, active layers, other interlayer dependencies)

Density Rules l Modern foundry rules specify layout density bounds to minimize impact of CMP on yield l Density rules control local feature density for w  w windows –e.g., for metal layer every 2000um  2000um window must be between 35% and 70% filled l Filling = insertion of "dummy" features to improve layout density –typically via layout post-processing in PV / TCAD tools –affects vital design characteristics (e.g., RC extraction) –accurate knowledge of filling is required during physical design and verification

Need for Density Awareness in Layout l Performance verification flow: l Filling/slotting geometries affect RC extraction RCXROM Delay Calc Timing/Noise Analysis l Up to 1% error in extracted capacitance l Reliability also affected (e.g. slotting of power stripes)

Need for Density Awareness in Layout l Performance verification flow: l Can be considered as ``single-layer’’ problem Caveat: contacting, active layers, other interlayer dependencies RCXROM Delay Calc Timing/Noise Analysis

Limitations of Current Techniques l Current techniques for density control have three key weaknesses: (1) only the average overall feature density is constrained, while local variation in feature density is ignored (2) density analysis does not find true extremal window densities - instead, it finds extremal window densities only over fixed set of window positions (3) fill insertion into layout does not minimize the maximum variation in window density

Layout Density Control Flow Density Analysis find total feature area in each window find maximum/minimum total feature area over all w  w windows Fill synthesis compute amounts, locations of dummy fill generate fill geometries find slack (available area for filling) in each window

Exact Max-Density Window Analysis l For each pivot rectangle R do –find density of w  w window W that abuts R on top and right –while W intersects R do –slide W right till intersection with other rectangle edge –record changes in density l O(k 2 ) algorithm for k rectangles R W

Fixed r-Dissection Regime l Feature area density bounds enforced only for fixed set of w  w windows l Layout partitioned by r 2 distinct fixed dissections l Each w  w window is partitioned in r 2 tiles tile overlapping windows fixed r-dissection with r = 4

Drawbacks of Fixed r-Dissection Analysis l If all w  w windows of fixed r-dissection have density  U, there may be floating w  w window with density min{1, U + 1/r -1/(4r 2 )} l Fixed-dissection algorithm is inaccurate l Exact algorithm is slow = O(k 2 )

Shrunk and Bloated Windows l Standard window = fixed r-dissection w  w window l Floating window = arbitrary w  w window l Bloated window = standard window bloated by one tile l Shrunk window = standard window shrunk by one tile l Any floating window is contained in one bloated window and contains one shrunk window standard window floating window shrunk window bloated window

Multilevel Approach l Estimation : –max floating window density  max bloated window density –min floating window density  min shrunk window density l Zooming: –remove standard windows in underfilled bloated windows –subdivide remaining tiles and find area of new bloated windows l Terminate subdivision when either : –# of rectangles is small (run exact density analysis), or –(max bloated density)/(max standard density)   (say,  = 1%)

Multilevel Algorithm Tiles = list of all windows (r =1) Accuracy =  While Accuracy > 1+  find are in each bloated and standard window MAX = max area of standard window BMAX = max area of bloated window refine Tiles = list of tiles from bloated windows of area  MAX subdivide each tile in Tiles into 4 subtiles Accuracy = BMAX / MAX Output max standard window density = MAX/ w 2

Runtime of Multilevel Algorithm l Each iteration decreases difference in area between bloated and standard window by half l Original difference is 3w 2 l Main loop terminates after t iterations: 3w 2 /2 t  2  l Maximum t is O(log(w/  ) l Runtime is O((n/w * log(w/  )) 2 )

Filling Problem l Given design rule-correct layout of k disjoint rectilinear features in n  n region l Find design rule-correct filled layout –no fill geometry is added within distance B of any layout feature –no fill is added into any window that has density  U –minimum window density in the filled layout is maximized (or has density  lower bound L)

Filling Problem in Fixed-Dissection Regime l Given –fixed r-dissection of layout –feature area[T] in each tile T –slack[T] = area available for filling in T –maximum window density U l Find total fill area p[T] to add in each T s.t. any w  w window W has density  U and min W  T  W (area[T] + p[T]) is maximized

Fixed-Dissection LP Formulation l Maximize M (lower bound on window density) l subject to: –For any tile T: 0  p[T]  pattern  slack[T] –For any window W:  T  W p[T]  U  w 2 M   T  W (p[T] + area[T]) (pattern = max achievable pattern area density)

Fixed-Dissection LP Formulation one variable and two constraints per tile two constraints per window

Multilevel LP Formulation l Use multilevel density analysis in LP l Tiles[r] = list of fixed r-dissection tiles from bloated windows of area  MAX l Saved tiles = subdivided Tiles[r] minus Tiles[r+1] l Saved windows = all standard windows W for which area is found l Multilevel LP uses only constraints for saved tiles and saved windows

Multilevel LP Formulation Saved tiles have different sizes: tiles with more feature area are more subdivided ML LP has one variable and two constraints per tile and two constraints per window

Floating Deviation LP Formulation l Floating deviation = the difference between max and min floating window density l Floating deviation  max bloated window density - min shrunk window density l Floating deviation LP: –For any bloated window W:  T  W p[T]  U  w 2 – For any shrunk window W: M   T  W (p[T] + area[T])

Floating Deviation LP Formulation one variable and two constraints per tile one constraint per bloated window one constraint per shrunk window

Hierarchical Density Control l Hierarchical filling = master cell filling Tile T Subcells Features C1C1 C2C2 Cell C Slack[C] Buffer

Hierarchical LP Formulation l For any cell instance C of master cell C and tile T,  [C,T] is portion of slack[C] in intersection of C with T:  [C,T] = slack(C  T)/slack[C] l New variable d[C] per each master cell C: d[C] = filling per master cell C l New constraints: –For total amount of filling added into tile T: p[T] =  C  T d[C]   [C,T] –For amount of filling added into each master cell C: 0  d[C]  pattern  slack[C]

Synthesis of Filling Patterns l Given area of filling pattern p[i,j], insert filling pattern into tile T[i,j] uniformly over available area l Desirable properties of filling pattern –uniform coupling to long conductors –either grounded or floating

Basket-Weave Pattern l Each vertical/horizontal crossover line has same overlap capacitance to fill

Grounded Pattern l Fill with horizontal stripes, then span with vertical lines

Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UCSD, UVA and GSU)

Outline l Chemical Mechanical Planarization & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

CMP and Interlevel Dielectric Thickness l Chemical-Mechanical Planarization (CMP) = wafer surface planarization l Uneven features cause polishing pad to deform Dummy features ILD thickness Interlevel-dielectric (ILD) thickness  feature density Insert dummy features to decrease variation ILD thickness Features

Objectives of Density Control l Objective for Manufacture = Min-Var minimize “window” density variation subject to upper bound on window layout density l Objective for Design = Min-Fill minimize total amount of filling subject to bound on window layout density variation

Filling Problem Statement l Given –rule-correct layout in n  n region – window size = w  w – window density upper bound U, buffer distance B l Add dummy fill to the layout with Min-Var and/or Min-Fill objective such that no fill is added –within given buffer distance B of any layout feature –into any overfilled window that already has density  U

Fixed-Dissection Regime l Monitor only fixed set of w  w windows – “offset” = w/r (example shown: w = 4, r = 4) l Partition n x n layout into overlapping fixed dissections l Each w  w window is partitioned into r 2 tiles Overlapping windows w w/r n tile

Layout Density Models l Spatial Density Model window density  sum of tiles feature area Slack Area Feature Area tile l Effective Density Model (more accurate) window density  weighted sum of tiles' feature area –weights decrease from window center to boundaries

Requirements for Dummy Filling l Estimation of RC parasitics, gate/interconnect delays and device reliability in PD & verification l Compatibility of master cell, macro characterizations with later insertion of dummy fill l Consistent with design hierarchy to avoid data explosion and maintain verifiability

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

Linear Programming Approaches l Min-Var Objective (Kahng et al.) –Maximize: M –Subject to : for any tile 0  p[T]  slack[T] for any window  T  W (p[T]+area[T])  U M   T  W (p[T] + area[T]) p[T] = fill area of tile –spatial density model l Min-Fill Objective (Wong et al.) –Minimize: fill amount –Subject to: for any tile 0  p[T]  slack[T] LowerB   0 (T)  UpperB MAX  0 (T) - MIN  0 (T)    0 (T) = effective density of tile T –effective density model

Monte-Carlo Approach l Min-Var objective –pick the tile for next filling geometry randomly –higher priority (based on max covering window density) of tile  higher probability to be filled –lock tile if any containing window is overfilled –update window priorities l Min-Fill objective –Fill-Deletion problem –delete as much fill as possible while maintaining min window density  L. –Min-Fill Monte-Carlo algorithm –if (min covering-window density < L) lock the tile –randomly select unlocked tile by its priority –delete a filling geometry from tile –update priorities of tiles

Iterated Monte-Carlo Approach l Repeat forever –run Min-Var Monte-Carlo with max window density U –exit if no change in minimum window density –run Min-Fill Monte-Carlo with min window density M No Improvement

LP vs. Monte-Carlo for Flat Filling l LP  impractical runtime for large layouts  r-dissection solution may be suboptimal for 2r dissections  essential rounding error for small tiles l Monte-Carlo  very efficient: O((nr/w)log(nr/w)) time  scalability: handle large values of r  accuracy: reasonably high comparing with LP

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

Hierarchical Filling Problem l Dummy fill are added only to master cells Two instances of a master cell Original layout features Flat fill solution Hierarchical fill solution l Each cell of the filled layout is a filled version of the corresponding original master cell

Why Hierarchical Filling? l Hierarchical characteristics of design flows l Enables and faster verification of the filled layout l Decreases data volume for

Challenges of Hierarchical Filling l Density constraints apply to all instances of the master l Interactions / interferences at master cell boundaries l Always gives worse results than flat solutions

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

Why Not LP? l Complexity caused by constraints –need a huge number of variables and constraints for each window, cell instance, and feasible fill position l Overlaps between cell instances –ownership of overlapping regions –unavailable regions for fill

Monte-Carlo Hierarchical Filling Original layout density analysis

Master cell Computing Slack Hierarchically buffer slack l Overlaps between  2 instances of different masters l Overlaps between master and features l Overlaps between  2 instances of the same master Exclude the overlapping regions

Drawbacks of Hierarchical Filling l Sparse or unfilled region in the solution –the overlaps –bloat regions features three instances of a master cell l Cause high layout density variation ! ! ! !

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

k-way Master Cell Splitting C1C1 CiCi C2C2 C2`C2` C1`C1` C1`C1` C2`C2` CiCi C2C2 C1C1 C i,1 C i,2 C1`C1` C2`C2` C2C2 C1C1 C1`C1` C2`C2` C i,1 C i,2 l Create k copies of master cell C i l k   : hierarchical layout  flat layout C2`C2` C1`C1` C2`C2` C1`C1` l Link contained master cells C` with new copies C1C1 C2C2 l Randomly replace C i in master cells with new copies

Hybrid Hierarchical / Flat Filling Purely hierarchical fill phase Flat fill `cleanup` phase Split-hierarchical phase features three instances of a master cell

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

Computational Experience l Testbed –GDSII input –hierarchical polygon database –C++ under Solaris l Test cases: Artificial hierarchical layouts based on single cell, different magnification factors l Implementation features –grid slack computation –doughnut area computation –wraparound density analysis and synthesis –different pattern types

Computational Experience Comparison among hierarchical, flat and hybrid filling approaches

Outline l Chemical-Mechanical Polishing & Filling Problem l Previous Works –Linear programming approaches –Monte-Carlo (MC) approaches l Our Contributions: –Hierarchical filling problem –Hierarchical filling algorithm –Hybrid hierarchical / flat filling approach l Computational Experience l Summary and Future Research

Summary and Future Research l Hierarchical filling problem for CMP uniformity l Practical pure hierarchical filling algorithm l Practical hybrid hierarchical filling approach –trade off runtime, solution quality and data volume l Ongoing research –Alternate pure hierarchical filling heuristics –Reusable solutions –Fill compression –Layer interactions (filling/cheesing, dual-material, …)

CMP in STI Process l Shallow Trench Isolation (STI) technique for isolation on the active layer in all deep submicron CMOS productions –deposit nitride layer on silicon –etch shallow trenches through nitride silicon –deposit oxide to fill trenches and cove nitride –remove excess oxide and partially nitride by CMP l Strong uniformity requirement for CMP in STI