Lecture 4: Spread Spectrum and Coding Anders Västberg Slides are a selection from the slides from chapter 7 and 8 from:

Multiple Access Techniques Frequency-division multiple access (FDMA) –Takes advantage of the fact that the useful bandwidth of the medium exceeds the required bandwidth of a given signal Time-division multiple access (TDMA) –Takes advantage of the fact that the achievable bit rate of the medium exceeds the required data rate of a digital signal

Frequency-division Multiplexing

Time-division Multiplexing

Spread Spectrum Input is fed into a channel encoder –Produces analog signal with narrow bandwidth Signal is further modulated using sequence of digits –Spreading code or spreading sequence –Generated by pseudonoise, or pseudo-random number generator Effect of modulation is to increase bandwidth of signal to be transmitted

Spread Spectrum On receiving end, digit sequence is used to demodulate the spread spectrum signal Signal is fed into a channel decoder to recover data

Spread Spectrum

What can be gained from apparent waste of spectrum? –Immunity from various kinds of noise and multipath distortion –Can be used for hiding and encrypting signals –Several users can independently use the same higher bandwidth with very little interference

Frequency Hoping Spread Spectrum (FHSS) Signal is broadcast over seemingly random series of radio frequencies –A number of channels allocated for the FH signal –Width of each channel corresponds to bandwidth of input signal Signal hops from frequency to frequency at fixed intervals –Transmitter operates in one channel at a time –Bits are transmitted using some encoding scheme –At each successive interval, a new carrier frequency is selected

Frequency Hoping Spread Spectrum Channel sequence dictated by spreading code Receiver, hopping between frequencies in synchronization with transmitter, picks up message Advantages –Eavesdroppers hear only unintelligible blips –Attempts to jam signal on one frequency succeed only at knocking out a few bits

Frequency Hoping Spread Spectrum

Frequency Hopping Spread Spectrum

FHSS Using MFSK MFSK (multiple FSK) signal is translated to a new frequency every T c seconds by modulating the MFSK signal with the FHSS carrier signal M=2 L where L is the number of bits in a signal element For data rate of R: –duration of a bit: T = 1/R seconds –duration of signal element: T s = LT seconds T c  T s - slow-frequency-hop spread spectrum T c < T s - fast-frequency-hop spread spectrum

Slow Frequency-Hop SS

Fast Frequency-Hop SS

FHSS Performance Considerations Large number of frequencies used Results in a system that is quite resistant to jamming –Jammer must jam all frequencies –With fixed power, this reduces the jamming power in any one frequency band

Direct Sequence Spread Spectrum (DSSS) Each bit in original signal is represented by multiple bits in the transmitted signal Spreading code spreads signal across a wider frequency band –Spread is in direct proportion to number of bits used One technique combines digital information stream with the spreading code bit stream using exclusive- OR (Figure 7.6)

Direct Sequence Spread Spectrum (DSSS)

DSSS Using BPSK Multiply BPSK signal, s d (t) = A d(t) cos(2  f c t) by c(t) [takes values +1, -1] to get s(t) = A d(t)c(t) cos(2  f c t) A = amplitude of signal f c = carrier frequency d(t) = discrete function [+1, -1] At receiver, incoming signal multiplied by c(t) –Since, c(t) x c(t) = 1, incoming signal is recovered

DSSS Using BPSK

Code-Division Multiple Access (CDMA) Basic Principles of CDMA –D = rate of data signal –Break each bit into k chips Chips are a user-specific fixed pattern –Chip data rate of new channel = kD

CDMA Example If k=6 and code is a sequence of 1s and -1s –For a ‘1’ bit, A sends code as chip pattern –For a ‘0’ bit, A sends complement of code Receiver knows sender’s code and performs electronic decode function = received chip pattern = sender’s code

CDMA Example User A code = –To send a 1 bit = –To send a 0 bit = User B code = –To send a 1 bit = Receiver receiving with A’s code –(A’s code) x (received chip pattern) User A ‘1’ bit: 6 -> 1 User A ‘0’ bit: -6 -> 0 User B ‘1’ bit: 0 -> unwanted signal ignored

CDMA for Direct Sequence Spread Spectrum

Categories of Spreading Sequences Spreading Sequence Categories –PN sequences –Orthogonal codes For FHSS systems –PN sequences most common For DSSS systems not employing CDMA –PN sequences most common For DSSS CDMA systems –PN sequences –Orthogonal codes

PN Sequences PN generator produces periodic sequence that appears to be random PN Sequences –Generated by an algorithm using initial seed –Sequence isn’t statistically random but will pass many test of randomness –Sequences referred to as pseudorandom numbers or pseudonoise sequences –Unless algorithm and seed are known, the sequence is impractical to predict

Important PN Properties Randomness –Uniform distribution Balance property Run property –Independence –Correlation property Unpredictability

Linear Feedback Shift Register Implementation

Properties of M-Sequences Property 1: –Has 2 n-1 ones and 2 n-1 -1 zeros Property 2: –For a window of length n slid along output for N (=2 n-1 ) shifts, each n-tuple appears once, except for the all zeros sequence Property 3: –Sequence contains one run of ones, length n –One run of zeros, length n-1 –One run of ones and one run of zeros, length n-2 –Two runs of ones and two runs of zeros, length n-3 –2 n-3 runs of ones and 2 n-3 runs of zeros, length 1

Properties of M-Sequences Property 4: –The periodic autocorrelation of a ±1 m- sequence is

PN Autocorrelation Function

Definitions Correlation –The concept of determining how much similarity one set of data has with another –Range between –1 and 1 1 The second sequence matches the first sequence 0 There is no relation at all between the two sequences -1 The two sequences are mirror images Cross correlation –The comparison between two sequences from different sources rather than a shifted copy of a sequence with itself

Advantages of Cross Correlation The cross correlation between an m-sequence and noise is low –This property is useful to the receiver in filtering out noise The cross correlation between two different m- sequences is low –This property is useful for CDMA applications –Enables a receiver to discriminate among spread spectrum signals generated by different m-sequences

Gold Sequences Gold sequences constructed by the XOR of two m- sequences with the same clocking Codes have well-defined cross correlation properties Only simple circuitry needed to generate large number of unique codes In following example (Figure 7.16a) two shift registers generate the two m-sequences and these are then bitwise XORed

Gold Sequences

Orthogonal Codes Orthogonal codes –All pairwise cross correlations are zero –Fixed- and variable-length codes used in CDMA systems –For CDMA application, each mobile user uses one sequence in the set as a spreading code Provides zero cross correlation among all users Types –Welsh codes –Variable-Length Orthogonal codes

Walsh Codes Set of Walsh codes of length n consists of the n rows of an n ´ n Walsh matrix: –W 1 = (0) n = dimension of the matrix –Every row is orthogonal to every other row and to the logical not of every other row –Requires tight synchronization Cross correlation between different shifts of Walsh sequences is not zero

Typical Multiple Spreading Approach Spread data rate by an orthogonal code (channelization code) –Provides mutual orthogonality among all users in the same cell Further spread result by a PN sequence (scrambling code) –Provides mutual randomness (low cross correlation) between users in different cells

Coping with Data Transmission Errors Error detection codes –Detects the presence of an error Automatic repeat request (ARQ) protocols –Block of data with error is discarded –Transmitter retransmits that block of data Error correction codes, or forward correction codes (FEC) –Designed to detect and correct errors

Error Detection Probabilities Definitions P b : Probability of single bit error (BER) P 1 : Probability that a frame arrives with no bit errors P 2 : While using error detection, the probability that a frame arrives with one or more undetected errors P 3 : While using error detection, the probability that a frame arrives with one or more detected bit errors but no undetected bit errors

Error Detection Probabilities With no error detection F = Number of bits per frame

Error Detection Process Transmitter –For a given frame, an error-detecting code (check bits) is calculated from data bits –Check bits are appended to data bits Receiver –Separates incoming frame into data bits and check bits –Calculates check bits from received data bits –Compares calculated check bits against received check bits –Detected error occurs if mismatch

Error Detection Process

Parity Check Parity bit appended to a block of data Even parity –Added bit ensures an even number of 1s Odd parity –Addedbit ensures an odd number of 1s Example, 7-bit character [ ] –Even parity [ ] –Odd parity [ ]

Cyclic Redundancy Check (CRC) Transmitter –For a k-bit block, transmitter generates an (n-k)-bit frame check sequence (FCS) –Resulting frame of n bits is exactly divisible by predetermined number Receiver –Divides incoming frame by predetermined number –If no remainder, assumes no error

CRC using Modulo 2 Arithmetic Exclusive-OR (XOR) operation Parameters: T = n-bit frame to be transmitted D = k-bit block of data; the first k bits of T F = (n – k)-bit FCS; the last (n – k) bits of T P = pattern of n–k+1 bits; this is the predetermined divisor Q = Quotient R = Remainder

CRC using Modulo 2 Arithmetic For T/P to have no remainder, start with Divide 2 n-k D by P gives quotient and remainder Use remainder as FCS

CRC using Modulo 2 Arithmetic Does R cause T/P have no remainder? Substituting, –No remainder, so T is exactly divisible by P

CRC using Polynomials All values expressed as polynomials –Dummy variable X with binary coefficients

CRC using Polynomials Widely used versions of P(X) –CRC–12 X 12 + X 11 + X 3 + X 2 + X + 1 –CRC–16 X 16 + X 15 + X –CRC – CCITT X 16 + X 12 + X –CRC – 32 X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1

CRC using Digital Logic Dividing circuit consisting of: –XOR gates Up to n – k XOR gates Presence of a gate corresponds to the presence of a term in the divisor polynomial P(X) –A shift register String of 1-bit storage devices Register contains n – k bits, equal to the length of the FCS

Digital Logic CRC

Wireless Transmission Errors Error detection requires retransmission Detection inadequate for wireless applications –Error rate on wireless link can be high, results in a large number of retransmissions –Long propagation delay compared to transmission time

Block Error Correction Codes Transmitter –Forward error correction (FEC) encoder maps each k-bit block into an n-bit block codeword –Codeword is transmitted; analog for wireless transmission Receiver –Incoming signal is demodulated –Block passed through an FEC decoder

Forward Error Correction Process

FEC Decoder Outcomes No errors present –Codeword produced by decoder matches original codeword Decoder detects and corrects bit errors Decoder detects but cannot correct bit errors; reports uncorrectable error Decoder detects no bit errors, though errors are present

Block Code Principles Hamming distance – for 2 n-bit binary sequences, the number of different bits –E.g., v 1 =011011; v 2 =110001; d(v1, v 2 )=3 Redundancy – ratio of redundant bits to data bits Code rate – ratio of data bits to total bits Coding gain – the reduction in the required E b /N 0 to achieve a specified BER of an error-correcting coded system

How Coding Improves Performance

Hamming Code Designed to correct single bit errors Family of (n, k) block error-correcting codes with parameters: –Block length:n = 2 m – 1 –Number of data bits: k = 2 m – m – 1 –Number of check bits: n – k = m –Minimum distance: d min = 3 Single-error-correcting (SEC) code –SEC double-error-detecting (SEC-DED) code

Hamming Code Process Encoding: k data bits + (n -k) check bits Decoding: compares received (n -k) bits with calculated (n -k) bits using XOR –Resulting (n -k) bits called syndrome word –Syndrome range is between 0 and 2 (n-k) -1 –Each bit of syndrome indicates a match (0) or conflict (1) in that bit position

Cyclic Codes Can be encoded and decoded using linear feedback shift registers (LFSRs) For cyclic codes, a valid codeword (c 0, c 1, …, c n-1 ), shifted right one bit, is also a valid codeword (c n-1, c 0, …, c n-2 ) Takes fixed-length input (k) and produces fixed- length check code (n-k) –In contrast, CRC error-detecting code accepts arbitrary length input for fixed-length check code

BCH Codes For positive pair of integers m and t, a (n, k) BCH code has parameters: –Block length: n = 2 m – 1 –Number of check bits: n – k  mt –Minimum distance:d min  2t + 1 Correct combinations of t or fewer errors Flexibility in choice of parameters –Block length, code rate

Reed-Solomon Codes Subclass of nonbinary BCH codes Data processed in chunks of m bits, called symbols An (n, k) RS code has parameters: –Symbol length: m bits per symbol –Block length: n = 2 m – 1 symbols = m(2 m – 1) bits –Data length: k symbols –Size of check code: n – k = 2t symbols = m(2t) bits –Minimum distance: d min = 2t + 1 symbols

Block Interleaving Data written to and read from memory in different orders Data bits and corresponding check bits are interspersed with bits from other blocks At receiver, data are deinterleaved to recover original order A burst error that may occur is spread out over a number of blocks, making error correction possible

Block Interleaving

Convolutional Codes Generates redundant bits continuously Error checking and correcting carried out continuously –(n, k, K) code Input processes k bits at a time Output produces n bits for every k input bits K = constraint factor k and n generally very small –n-bit output of (n, k, K) code depends on: Current block of k input bits Previous K-1 blocks of k input bits

Convolutional Encoder

Decoding Trellis diagram – expanded encoder diagram Viterbi code – error correction algorithm –Compares received sequence with all possible transmitted sequences –Algorithm chooses path through trellis whose coded sequence differs from received sequence in the fewest number of places –Once a valid path is selected as the correct path, the decoder can recover the input data bits from the output code bits

Trellis Diagram

Trellis diagram

Viterbi algorithm

Automatic Repeat Request Mechanism used in data link control and transport protocols Relies on use of an error detection code (such as CRC) Flow Control Error Control

Flow Control Assures that transmitting entity does not overwhelm a receiving entity with data Protocols with flow control mechanism allow multiple PDUs in transit at the same time PDUs arrive in same order they’re sent Sliding-window flow control –Transmitter maintains list (window) of sequence numbers allowed to send –Receiver maintains list allowed to receive

Flow Control Reasons for breaking up a block of data before transmitting: –Limited buffer size of receiver –Retransmission of PDU due to error requires smaller amounts of data to be retransmitted –On shared medium, larger PDUs occupy medium for extended period, causing delays at other sending stations

Flow Control

Error Control Mechanisms to detect and correct transmission errors Types of errors: –Lost PDU : a PDU fails to arrive –Damaged PDU : PDU arrives with errors

Error Control Requirements Error detection –Receiver detects errors and discards PDUs Positive acknowledgement –Destination returns acknowledgment of received, error- free PDUs Retransmission after timeout –Source retransmits unacknowledged PDU Negative acknowledgement and retransmission –Destination returns negative acknowledgment to PDUs in error

Go-back-N ARQ Acknowledgments –RR = receive ready (no errors occur) –REJ = reject (error detected) Contingencies –Damaged PDU –Damaged RR –Damaged REJ

Go-back N ARQ