1 Timing-Driven Synthesis for Fast Barrel Shifters Sabyasachi Das University of Colorado, Boulder Sunil P. Khatri Texas A&M University

2 What is a Shifter? IC block that performs shifting of data signals IC block that performs shifting of data signals Well-known logic architectures Well-known logic architectures Computationally-intensive Computationally-intensive Occupies significant amount of area Occupies significant amount of area Wide usage in DSP, Graphics, Microprocessors Wide usage in DSP, Graphics, Microprocessors

3 Introduction to Barrel Shifter Widely used Shifter architecture Widely used Shifter architecture Exhibits good timing characteristic Exhibits good timing characteristic Area-efficient as well Area-efficient as well Inherent regularity in physical structure Inherent regularity in physical structure

4 Structure of Barrel Shifter Width of input and output data signals = n bits Width of input and output data signals = n bits Width of input shift signal = log 2 n bits Width of input shift signal = log 2 n bits Shifter consists of log 2 n stages Shifter consists of log 2 n stages Each bit of the shift signal controls one stage Each bit of the shift signal controls one stage Each stage handles single shift of 0 or 2 i bits Each stage handles single shift of 0 or 2 i bits

5 Example of a Barrel Shifter (2-stage) S 0 = 1’b1 s0s0 x 2 x 1 s0s0 x 3 x 2 s 0 x 0 1’b0 s0s0 x 1 x 0 s1s1 s1s1 s1s1 s1s1 1’b0 z0z0 z3z3 z2z2 z1z1 S 1 = 1’b0 1’b0 x0x0 x1x1 x2x2 x2x2 x1x1 x0x0

6 Proposed Dual-Merged Stage Merge stages i and j Merge stages i and j 4 bit input data signal 4 bit input data signal 2 bit shift signal 2 bit shift signal i and j do not need to be two consecutive bits of the shift signal i and j do not need to be two consecutive bits of the shift signal x a x b x c x d sisi sjsj z ij

7 Proposed Dual-Merged Stage For the q th BitSlice (Column) of a left shifter For the q th BitSlice (Column) of a left shifter x a = x q x a = x q x b = x (q- 2 i ) x b = x (q- 2 i ) x c = x (q- 2 j ) x c = x (q- 2 j ) x d = x (q- 2 i - 2 j ) x d = x (q- 2 i - 2 j ) For the q th BitSlice (Column) of a right shifter For the q th BitSlice (Column) of a right shifter x a = x q x a = x q x b = x (q+ 2 i ) x b = x (q+ 2 i ) x c = x (q+ 2 j ) x c = x (q+ 2 j ) x c = x (q+ 2 i + 2 j ) x c = x (q+ 2 i + 2 j )

8 Example of a 2-Stage Shifter Using Dual-Merged Stages s0s0 x 3 x 2 x 1 x 0 s 1 z 3 s0s0 s 1 z 2 s0s0 s 1 z 1 s0s0 s 1 z 0 x 2 x 1 x 0 0 x 1 x x S 1 S 0 = 2’b01 x1x1 x2x2 x0x0 1’b0

9 Proposed Triple-Merged Stage Merge stages i, j and k Merge stages i, j and k 8 bit input data signal 8 bit input data signal 3 bit shift signal 3 bit shift signal i, j and k do not need to be three consecutive bits of the shift signal i, j and k do not need to be three consecutive bits of the shift signal x e x f x g x h sisi sjsj z ijk sksk x a x b x c x d

10 Triple-Merged Stages For the q th BitSlice (Column) of a left shifter For the q th BitSlice (Column) of a left shifter x a = x q x a = x q x b = x (q- 2 i ) x b = x (q- 2 i ) x c = x (q- 2 j ) x c = x (q- 2 j ) x d = x (q- 2 k ) x d = x (q- 2 k ) x e = x (q- 2 i - 2 j ) x e = x (q- 2 i - 2 j ) x f = x (q- 2 i - 2 k ) x f = x (q- 2 i - 2 k ) x g = x (q- 2 j - 2 k ) x g = x (q- 2 j - 2 k ) x h = x (q- 2 i - 2 j - 2 k ) x h = x (q- 2 i - 2 j - 2 k )

11 Identification of Mergeable Stages Timing-driven algorithm Timing-driven algorithm Uses arrival-time of the shift signals Uses arrival-time of the shift signals Uses the timing characteristic of the technology library cells Uses the timing characteristic of the technology library cells

12 Algorithm to Find Mergeable Stages Sort shift signals by arrival time (S i, S j, S k are earliest) Sort shift signals by arrival time (S i, S j, S k are earliest) Analyze dual-merged stage, triple-merged stage and unmerged stage to decide whether Analyze dual-merged stage, triple-merged stage and unmerged stage to decide whether To create a triple-merged stage by merging stages i, j and k To create a triple-merged stage by merging stages i, j and k To create a dual-merged stage by merging stages i and j To create a dual-merged stage by merging stages i and j To create an unmerged stage for the stage i To create an unmerged stage for the stage i Continue analysis with the next three stages corresponding to the 3 earliest arriving shift bits. Continue analysis with the next three stages corresponding to the 3 earliest arriving shift bits.

13 Analysis of an Unmerged Stage sisi x a x b sjsj sksk Arr_T(s k ) xcxc xdxd Arr_T(s j ) Arr_T(s i ) T single Compute the impact of an unmerged stage (i) Compute the impact of an unmerged stage (i) T single = Arr_T (si) + Del 1 T single = Arr_T (si) + Del 1

14 Analysis of Two Unmerged Stages sisi x a x b sjsj sksk Arr_T(s k ) xcxc xdxd Arr_T(s j ) Arr_T(s i ) T single2 Compute the impact of 2 cascaded unmerged stages Compute the impact of 2 cascaded unmerged stages Arr_T (s j ) T single2 = Max (T single, Arr_T (s j )) + Del 1

15 Analysis of Three Unmerged Stages sisi x a x b sjsj sksk Arr_T(s k ) xcxc xdxd Arr_T(s j ) Arr_T(s i ) T single3 Compute the impact of 3 cascaded unmerged stages Compute the impact of 3 cascaded unmerged stages Arr_T (s k ) T single3 = Max (T single2, Arr_T (s k )) + Del 1

16 Analysis of a Dual-merged Stage Arr_T(s i ) T dual Compute the impact of a dual-merged stage (i, j) Compute the impact of a dual-merged stage (i, j) T dual = Arr_T (s j ) + Del 2 T dual = Arr_T (s j ) + Del 2 x a x b x c x d sisi sjsj z ij Arr_T(s j )

17 Analysis of a Triple-merged Stage Arr_T(s i ) T triple Compute the impact of a triple-merged stage (i, j, k) Compute the impact of a triple-merged stage (i, j, k) T triple = Arr_T (s k ) + Del 3 T triple = Arr_T (s k ) + Del 3 Arr_T(s j ) x e x f x g x h sisi sjsj z ijk sksk x a x b x c x d Arr_T(s k )

18 Selection of Mergeable Stages If (T triple <) and (T triple <( + /2)) If (T triple <T single3 ) and (T triple <(T dual + Del 1 /2)) Implement triple-merged stage (for stages i, j and k) Implement triple-merged stage (for stages i, j and k) Else if (T dual <) Else if (T dual <T single2 ) Implement dual-merged stage (for stages i and j) Implement dual-merged stage (for stages i and j) Else Else Implement single unmerged stage for stage i Implement single unmerged stage for stage i

19 Results On an average, 10.19% faster than the result of the commercial Datapath Synthesis tool

20 Summary Merge 2 stages to form Dual-Merged stage Merge 2 stages to form Dual-Merged stage Merge 3 stages to form Triple-Merged stage Merge 3 stages to form Triple-Merged stage Timing-driven algorithm to identify mergeable stages Timing-driven algorithm to identify mergeable stages Reduces the number of stages upto one-third (33.33%) Reduces the number of stages upto one-third (33.33%) On an average, 10.19% faster On an average, 10.19% faster

21 Thank you