Very low power pipelines using significance compression Canal, R. Gonzalez, A. Smith, J.E. Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain 33rd Annual IEEE/ACM International Symposium 2000, pp

2/ /11/25 Very low power pipelines using significance compression Abstract  Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This significance compression method is integrated into a 5-stage pipeline, with the extension bits flowing down the pipeline to enable pipeline operations only for the significant bytes. Consequently, register logic and cache activity (and dynamic power) are substantially reduced.

3/ /11/25 Very low power pipelines using significance compression Abstract (cont.)  An initial trace-driven study shows reduction in activity of approximately 30-40% for each pipeline stage. Several pipeline organizations are studied. A byte serial pipeline is the simplest implementation, but suffers a CPI (cycles per instruction) increase of 79% compared with a conventional 32-bit pipeline. Widening certain pipeline stages in order to balance processing bandwidth leads to an implementation with a CPI 24% higher than the baseline 32-bit design. Finally, full-width pipeline stages with operand gating achieve a CPI within 2-6% of the baseline 32-bit pipeline.

4/ /11/25 Very low power pipelines using significance compression What’s the problem?  Energy consumption is the most critical design constraint in some microprocessor applications  For example, energy saving is more important than performance in the battery-powered embedded applications

5/ /11/25 Very low power pipelines using significance compression Introduction for reducing activity level  Dynamic energy consumption is proportional to the switching activity  gate off some execute unit if no use  reduce the activity of memory access

6/ /11/25 Very low power pipelines using significance compression Data representation  The data has only a few numerically significant low-order bits  for example, two’s complement integer data  use two extension bits to compress  ex > 04:11  ex. FF FF F5 04 -> F5 04 : 10  The address data usually has some internal bits that are insignificant  use three extension bits to compress  ex > : 011  ex. FF E > E7 04 : 101

7/ /11/25 Very low power pipelines using significance compression PC increment  using block-serial implementation  higher order bits is not often changed  block size N can be change : 1~30bit(s)  N=5 activity is reduced by 83% performance loss 3%

8/ /11/25 Very low power pipelines using significance compression Instruction cache  R-format : recode function field and exchange shift field  eight common cases using three bits function  shift do not use the rs field  I-format : divide immediate field into 2 parts  59.1%use immediate value and 80% only need 8 bits

9/ /11/25 Very low power pipelines using significance compression ALU operations  case 1 : both bytes are significant  byte addition must be perform  case 2 : one of the operands has a significant byte  Non-significant byte 0(1) carry-in 0(1) : equal to significant byte  Non-significant byte 0(1) carry-in 1(0) : significant byte plus 1 (minus one)  case 3 : neither of the operands has a significant byte in the position being added  depend on C i-1

10/ /11/25 Very low power pipelines using significance compression ALU operations (cont.)  A i and B i are both sign extensions of their preceding bytes,A i-1 and B i-1  C i =A i +B i  In general, C i is not significant  In the exceptional cases, ALU general a full byte value

11/ /11/25 Very low power pipelines using significance compression Data cache operation  extension bits are appended to each data word  the bytes containing significant data are read and write  first compared with low order tag, if not match, early miss can be signaled  miss rate is always low, the method is not efficient

12/ /11/25 Very low power pipelines using significance compression Activity performance

13/ /11/25 Very low power pipelines using significance compression Byte-serial implementation  one byte wide data path  multiple cycles for data if needs  one byte wide PC increment unit  three byte wide instruction cache  avoid excessive stalls

14/ /11/25 Very low power pipelines using significance compression Byte-serial implementation (cont.)  Byte-serial implementation

15/ /11/25 Very low power pipelines using significance compression Semi-parallel implementation  reduce performance losses  two byte-wide register files  multiple byte-wide ALU  it can be disabled if it is no use  add extra pipeline stage  72% of stalls are caused by structural hazards in the EX stage

16/ /11/25 Very low power pipelines using significance compression Semi-parallel implementation (cont.)  Byte semi-parallel implementation

17/ /11/25 Very low power pipelines using significance compression Fully parallel implementation  Byte-parallel skewed pipeline  4 bytes parallelism at each stage  similar way to the semi-parallel implementation  is optimized for the long data cases  Byte-parallel compressed pipeline  4 bytes parallelism at each stage  consists of the original 5 stages  one more cycle in the same stage to read addition data  store only use a single cycle  works well for short data

18/ /11/25 Very low power pipelines using significance compression Fully parallel implementation (cont.)  Two fully parallel implementations

19/ /11/25 Very low power pipelines using significance compression Performance of three implementations

20/ /11/25 Very low power pipelines using significance compression Conclusion  It proposed a number of pipeline implementations that achieve these low activity levels while providing a reasonable level of performance