DANDE CDH PDRECEN 4610 Capstone Laboratory D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling (CDH) Critical Design Review October 11 th, 2007 Brandon Gilles (EE) James Gorman (ECE) Eric McIntyre (ECE) Gabriel Thatcher (EE)

DANDE CDH PDRECEN 4610 Capstone Laboratory System Architecture Review 2

DANDE CDH PDRECEN 4610 Capstone Laboratory Overview of Current Status Completed ‘Meter-Stones’ –8-bit board ordered. –New Linux Kernel running. –I 2 C driver compiled, loaded, and O-scope tested. –32-bit board up and running with new Kernel. –Software Use Cases and Software Requirements (SRS) Specification Fully defined Approved by DANDE management.

DANDE CDH PDRECEN 4610 Capstone Laboratory Overview of Current Status In the Works –8-bit board assembly and test. –8-bit software architecture. Library support package Bus-messaging driver –32-bit software modeling Architecture, Object, and Sequence Models Needs Attention –Watchdog Circuitry

DANDE CDH PDRECEN 4610 Capstone Laboratory Hardware Subsystems

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Schematics

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Schematics

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Board Overview

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Board Overview

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Board Visualization

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Board Visualization

DANDE CDH PDRECEN 4610 Capstone Laboratory Hardware Central Processor

DANDE CDH PDRECEN 4610 Capstone Laboratory 32-bit Board Build or Buy Decision: Buy Atmel NGW100 Reference Design ~ $80

DANDE CDH PDRECEN 4610 Capstone Laboratory Why? Software Development Schedule Man-hours desperately needed Already hard-pressed to finish software Cost-Benefit Analysis NGW100 meets most requirements Large development time and cost Atmel needed 8-layers to implement NGW ping BGA package

DANDE CDH PDRECEN 4610 Capstone Laboratory Software

DANDE CDH PDRECEN 4610 Capstone Laboratory Software Development Cycle Use-cases Requirements Definitions Requirements Approval Architectural Support Object Model Sequence Model Buildable Stub Iterative Testing Final Implementation Completed – 9/15 Completed – 9/24 Completed – 10/1 ~Completed In Progress Not Started

DANDE CDH PDRECEN 4610 Capstone Laboratory 32-bit Software Architecture

DANDE CDH PDRECEN 4610 Capstone Laboratory Data Flows Housekeeping DataScience Data

DANDE CDH PDRECEN 4610 Capstone Laboratory Subsystem Communication I 2 C link to subsystems Standardized Transmission Format across all subsystems Communication done through Bus Messenger via IPC

DANDE CDH PDRECEN 4610 Capstone Laboratory Boot-Up Sequence

DANDE CDH PDRECEN 4610 Capstone Laboratory Project Goals

DANDE CDH PDRECEN 4610 Capstone Laboratory Project Goals Milestone 1 Goals Subsystem board and support code complete Software analysis complete –Architecture Support –Object Model –Sequence Model Stub of 32-bit software compiled Milestone 2 Goals 32-bit Software –80% functionality based on SRS –Test iteration 2 of 4 complete 8-bit to 32-bit integration complete

DANDE CDH PDRECEN 4610 Capstone Laboratory Project Goals Open-Lab Expo 32-bit software –100% functionality based on SRS –Test iteration 4 of 4 complete 8-bit to 32-bit communication at 100% Demo of Mach Satellite Operation –Central Processor –Two Subsystems –Intercommunication and Control

DANDE CDH PDRECEN 4610 Capstone Laboratory Current Division of Labor Brandon Gilles –Project Manager –REA - Linux Kernel – REA - 32-bit Hardware James Gorman –REA - 8-bit Hardware and Software Reference Design –REA - Watch Dog and Long Dog Circuitry 24 Across the board 32-bit Software Analysis, Design and Implementation Eric McIntyre –REA - 32-bit Software –Architecture –Analysis and Design –Implementation Gabriel Thatcher – REA - Memory Voting Logic –REA - Subsystem Hardware Interfacing REA - Responsible Engineering Authority Time Permitting De-Scope

DANDE CDH PDRECEN 4610 Capstone Laboratory Backup Slides

DANDE CDH PDRECEN 4610 Capstone Laboratory Parts List Overview What we have 3 NGW100s –Central Processor Boards 2 STK500s –Subsystem Programming Boards What we Need 2 Subsystem Boards (arriving today) –Reference Design for subsystem Developers

DANDE CDH PDRECEN 4610 Capstone Laboratory Detailed Parts List

DANDE CDH PDRECEN 4610 Capstone Laboratory Schedule

DANDE CDH PDRECEN 4610 Capstone Laboratory 32-bit Schematics

DANDE CDH PDRECEN 4610 Capstone Laboratory 32-bit Schematics

DANDE CDH PDRECEN 4610 Capstone Laboratory Exploded Satellite View

DANDE CDH PDRECEN 4610 Capstone Laboratory 32 Functional Block Diagram ACC Control Acc THM Control Coatings, Insulation Sensors Instrument NMS Control Instrument FOV 32° x 1° Instrument FOV 32° x 1° CDH I 2 C I/O CPU AVR32 RAM TBD SSD TBD RTC SFT OS Scheduling Comm ADCS Science Serial I/O Wiring Harness SEP Mech1 Mech2 Control Lightband assy. ABS EPS Photovoltaics 30W Battery B 14.4V 4AH RegulationControl FOV 360° Inhibit x4 Battery A 14.4V 4AH LV electrical interface Satellite Sep Plane (SSP) COM Tx Ant Rx Ant FOV 90° Tx 70cm 38.4kbps Rx 2m 9.6kbps TNC ACC Control Acc ADC Control Horizon Crossing Sensor Torque rod A Horizon Crossing Sensor Torque rod A Mag (3- axis) FOV 2° Instrument NMS Control Instrument FOV 32° x 1° Instrument FOV 32° x 1° ADC Control Horizon Crossing Sensor Torque rod A Horizon Crossing Sensor Torque rod A Mag (3- axis) FOV 2° THM Control Coatings, Insulation Sensors CDH I 2 C I/O CPU AVR32 RAM TBD SSD TBD RTC SFT OS Scheduling Comm ADCS Science Serial I/O EPS Photovoltaics 30W Battery B 14.4V 4AH RegulationControl FOV 360° Inhibit x4 Battery A 14.4V 4AH LV electrical interface Satellite Sep Plane (SSP) COM Tx Ant Rx Ant FOV 90° Tx 70cm 38.4kbps Rx 2m 9.6kbps TNC SEP Mech1 Mech2 Control Lightband assy. ABS