10/1/2004EECS150 Lab Lecture #51 Good Design & Network Audio EECS150 Fall2004 – Lab Lecture #5 Udam Saini

10/1/2004EECS150 Lab Lecture #52 Today (1) Synplify Warnings ChipScope Administrative Info

10/1/2004EECS150 Lab Lecture #53 Today (2) Lab #5: Network Audio Network Organization Ethernet Packets Eth2Audio Async FIFO

10/1/2004EECS150 Lab Lecture #54 Synplify Warnings (1) Why Bother? Part of your project grade Major warnings will cost points Knowing these will make your life easier Saves debugging Incomplete Sensitivity List ModelSim will use the sensitivity list Synplify pretty ignores it

10/1/2004EECS150 Lab Lecture #55 input[15:0]A, B; output[31:0]Sum; outputCOut; // Adder (A) {Sum, COut} = A + B; Synplify Warnings (2) inputClock; reg[31:0]Count; // Counter (posedge Clock) Count <= Count + 1; input[15:0]A, B; output[31:0]Sum; outputCOut; // Adder (A) {Sum, COut} = A + B; OK! Incomplete Sensitivity input[15:0]A, B; output[31:0]Sum; outputCOut; // Adder (A or B) {Sum, COut} = A + B; OK!

10/1/2004EECS150 Lab Lecture #56 Synplify Warnings (3) Latch Generated input[1:0]select; inputA, B, C; outputOut; regOut; // Mux (select or A or B or C) begin case (select) 2’b00: Out = A; 2’b01: Out = B; 2’b10: Out = C; endcase end input[1:0]select; inputA, B, C; outputOut; regOut; // Mux (select or A or B or C) begin case (select) 2’b00: Out = A; 2’b01: Out = B; 2’b10: Out = C; default: Out = 1’bx; endcase end

10/1/2004EECS150 Lab Lecture #57 Synplify Warnings (4) Combinational Loop Must remove the loop or add a register Synplify wont show you the loop Comment out code till it goes away ∞??

10/1/2004EECS150 Lab Lecture #58 Synplify Warnings (5) FPGA_TOP2 always has warnings Un-driven Input Unconnected Output These are truly unneeded pins Things like the audio chips… In your modules these are a problem Synplify will optimize your design Unconnected modules removed

10/1/2004EECS150 Lab Lecture #59 Synplify Warnings (6) Why bother? Getting rid of warnings saves debugging Synplify warnings will result in lost points Warnings are the only syntax check Verilog is a forgiving language Undeclared variables default to 1 bit wires This isn’t a good thing

10/1/2004EECS150 Lab Lecture #510 ChipScope (1) Software based logic analyzer Get results on the computer Put a logic analyzer right into the FPGA ICON – Connects FPGA to software ILA – Does the actual analysis More flexible than the bench analyzers But not as timing accurate

10/1/2004EECS150 Lab Lecture #511 ChipScope (2) Steps to use ChipScope Generate an ICON Generate an ILA Connect the ILA to the ICON Synthesize, and implement your design With the ILA and ICON Program the CaLinx board Run the ChipScope Pro Analyzer Runs over the JTAG not Slave Serial

10/1/2004EECS150 Lab Lecture #512 ChipScope (3) Logic Analyzer Similarities/Differences Triggering is similar Can be set to show waves before trigger Can trigger on repeated or combined events Data/Trigger can be MUCH bigger Up to 256bits wide As many samples as Block RAM on the FPGA Data is captured synchronously Can’t look at clocks Much easier to view waveforms

10/1/2004EECS150 Lab Lecture #513 ChipScope (4) ChipScope is useful to verify In this lab we’re using it just to make absolutely sure You will NEED ChipScope You cannot debug a large design without it Bench analyzers wont show enough signals Detailed ChipScope Tutorial Tutorials Tutorials

10/1/2004EECS150 Lab Lecture #514 Administrative Info Midterm I Midterm I completely graded Some have been handed back in discussion section. We will hand them out after Lab Lecture

10/1/2004EECS150 Lab Lecture #515 Lab #5: Network Audio Play Audio off Ethernet Receive Ethernet packets Decode and remove header Filter packets Play audio data payload A Major Project Given: Ethernet, Audio, ETC To be written: Packet Decode & Filtering

10/1/2004EECS150 Lab Lecture #516 Network Organization (1)

10/1/2004EECS150 Lab Lecture #517 Network Organization (2) DO NOT MODIFY THE PRODUCTION NETWORK

10/1/2004EECS150 Lab Lecture #518 Ethernet Packets (1) We’re using raw Ethernet No TCP/IP, its too complex Cant use this on the internet Raw Ethernet: 48bit Destination MAC Address 48bit Source MAC Address 16bit Ethernet Type Payload 32bit CRC

10/1/2004EECS150 Lab Lecture #519 Ethernet Packets (2) A Little Theory of Ethernet Bit Serial 100Mbps Link 4/5bit Encoding takes 20% overhead Bit5 is used for Data-Valid and Error Preamble used for clock extraction Inter Frame Gap ensures packets aren’t back-to-back CRC used to avoid errors from transmission

10/1/2004EECS150 Lab Lecture #520 Ethernet Packets (3)

10/1/2004EECS150 Lab Lecture #521 Ethernet Packets (4) A Good Packet Total: 1028x 32bit Words 48bit Destination (0xFFFFFFFFFFFF) 48bit Source (0x0090c2001c50) 16bit Packet Type (0x0101) 16bit Padding (0x????) 1024x 32bit PCM Audio Data

10/1/2004EECS150 Lab Lecture #522 Ethernet Packets (4) A Bad Packet Who knows how long? Source and Destination could be anything Packet Type probably not 0x0101 Coping with bad packets Do NOT send them to AudioTop Just keep dropping data until end of packet InPacketValid & InPacketInvalid

10/1/2004EECS150 Lab Lecture #523 Lab #5: Eth2Audio

10/1/2004EECS150 Lab Lecture #524 Lab #5: Eth2Audio SignalWidthDirDescription DIn 32IData from MAC_Top InValid 1IIndicates DIn is valid InPacketValid 1IIndicates the end of a good(crc) packet InPacketInvalid 1IIndicates the end of a bad(crc) packet EthernetClock 1I25MHz Ethernet Clock EthernetReset 1IEthernetClock sync. Reset AudioClock 1I12.288MHz Audio Clock AudioReset 1IAudioClock sync. Reset DOut 32OData out to AudioTop OutRequest 1IAudioTop requesting a new word OutValid 1OIndicates DOut is valid

10/1/2004EECS150 Lab Lecture #525 Lab #5: Eth2Audio Design Word Counter How many bits wide? Efficient Comparisons? Valid Register Stores whether the packet is valid or not Reset When do you reset word counter and valid register? Short and Long Bad Packets

10/1/2004EECS150 Lab Lecture #526 Lab #5: Eth2Audio Testing We give you a very nice testbench Read Lab5Testbench.v Read Lab5TestPackets.txt Fix your module in simulation Checkoff We should hear nice clean audio Show us your module using ChipScope

10/1/2004EECS150 Lab Lecture #527 Lab #5: Async FIFO Buffer to match two data rates Great for data path clock domain crossings Write on one clock Read on another Good place to buffer audio

9/28/2007EECS150 Lab Lecture #528 Verilog Tips & Tricks

EECS150 Lab Lecture #529 Running a New Simulation without Closing ModelSim In the ModelSim console, press the up arrow to see the previous command: {do xyzTestbench.fdo} This command will “recompile” your Verilog files and rerun the simulation. Rerunning without recompiling: restart –f; run 10us;

EECS150 Lab Lecture #530 Viewing Signals in Submodules Expand submodules in Workspace pane Click-and-drag signals to waveform Type “restart –f; run 10us;” in console. Do not use the “do” command!

EECS150 Lab Lecture #531 Declaring reg for outputs. Suppose count needs to be assigned a value in an always blocks. output [3:0] count; reg count; What’s wrong here? output [3:0] count; reg [3:0] count; What’s the best way of fixing this? output reg [3:0] count;

EECS150 Lab Lecture #532 Explicitly Connect to Module Ports We’ve been calling this “dot notation” Good: adder my_adder(.A(A),.B(B),.Sum(Sum)); Bad: adder my_adder(A,B,Sum);

EECS150 Lab Lecture #533 What Can Go Wrong? (1) Suppose David and Randy are working on a project. David writes module foo(A,B,F) Randy instantiates it in his design: wire w1,w2,w3; foo my_foo(w1, w2, w3);

EECS150 Lab Lecture #534 What Can Go Wrong? (2) David needs to add port C to foo: module foo(A,B,C,F) David tells Randy about the new port: wire w1,w2,w3,w4; foo my_foo(w1,w2,w3,w4); Now w3 connects to C instead of F!

EECS150 Lab Lecture #535 Use Meaningful Wire Names Bad wire w1, w2, w3; foo my_foo(.A(w1),.B(w2),.F(w3)); Good wire foo_a, foo_b, foo_f; foo my_foo(.A(foo_a),.B(foo_b),.F(foo_f)); More helpful when using ModelSim

EECS150 Lab Lecture #536 Synthesis Warnings In particular, watch out for these Combinational loop detected Latch generated Incomplete sensitivity list If any of these appear in your synthesis warnings, your synthesized design will most likely not match simulation.

EECS150 Lab Lecture #537 One Module per File Module name should match file name Otherwise, it’s difficult to find the file containing your module.

EECS150 Lab Lecture #538 blocks For state machines, use 2 or 3 always blocks. Recall the Mealy Machine: Output and Next State Combinational Logic InputsOutputs Next StateCurrent State State

EECS150 Lab Lecture #539 blocks (CurrentState or Inputs) begin NextState = CurrentState; Outputs = 0; case(CurrentState) STATE_Init: begin (Next state and output calculations here) end … endcase end (posedge Clock) if(Reset) CurrentState <= STATE_Init; else CurrentState <= NextState; Output and Next State Combinational Logic InputsOutputs Next StateCurrent State State

EECS150 Lab Lecture #540 blocks What about a Moore Machine? State transition part is the same May use three always blocks: (CurrentState or Inputs) begin NextState = CurrentState; case(CurrentState) [Calculate Next State] endcase end (CurrentState) begin Outputs = 0; case(CurrentState) [Calculate Output] endcase end

EECS150 Lab Lecture #541 More Moore Machines Suppose output “foo” is only high in state STATE_Foo: (CurrentState) begin foo = 0; case(CurrentState) … STATE_Foo: foo = 1; … endcase end May also use assign statements: assign foo = (CurrentState == STATE_Foo);

EECS150 Lab Lecture #542 Parameters as State Names Bad case(CurrentState) 3’b000: NextState = 3’b101; 3’b001: NextState = 3’b100; … endcase Good parameter STATE_Init = 3’b000, STATE_Foo = 3’b001, … case(CurrentState) STATE_Init: NextState = STATE_Bar; STATE_Foo: NextState = STATE_Baz; … endcase Parameters make your code easier to read, debug, and change.

EECS150 Lab Lecture #543 Use defparam Suppose you need a 6-bit register. In Register.v: Parameter width = 32; … Output [width-1:0] Out; Do not simply make a file called Register6.v and change the width! Instead, use defparam: Register MyRegister( … ); defparam MyRegister.width = 6;

EECS150 Lab Lecture #544 Use Register.v and Counter.v Suppose you need a counter that increments to 42 before resetting. // Without Counter.v (posedge Clock) if(Reset || (Count == 41)) Count <= 0; else if(Enable) Count <= Count + 1; // With Counter.v Counter MyCounter(.Clock(Clock),.Reset(Reset || (Count == 41),.Set(1’b0),.Load(1’b),.Enable(Enable),.In(0),.Count(Count)); defparam MyCounter.width = 6; Cleaner “always” blocks Don’t forget defparam!

EECS150 Lab Lecture #545 Avoid this Loop 1. Observe error on board 2. Make guess about source of error 3. Make small change to verilog files 4. Generate programming file (may take up to 20 minutes) 5. Surf Facebook 6. Go back to step 1 Instead, review your synthesis warnings and use Chipscope to debug. This is why some projects take 100+ hours

EECS150 Lab Lecture #546 Questions?