Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 11 - Data Communications 2 Fall 2007 Quiz Friday Verilog ASM Diagrams Design Readings (S&R Ch. 1-5, Colwell Ch. 1-3)

ECE 491 Fall 2007Lecture 13 - More Data Comm.2 Where we are  Last Week:  Data Communciations 1  ASM Diagrams  System Design  Today:  Serial Data Receiver  Serial Transmission Codes

ECE 491 Fall 2007Lecture 13 - More Data Comm.3 Lab 4 - RS-232 Transmitter Transmitter DATA START READY TxD CLK

ECE 491 Fall 2007Lecture 13 - More Data Comm.4 Receiver Design - Challenges  Sender and Recever are not synchronized (they run off separate clocks)  But, the transmission rate is known and fixed  Use this fact + start bit to do a limited form of clock recovery SR SCLKRCLK

ECE 491 Fall 2007Lecture 13 - More Data Comm.5 Lab 5 - RS-232 Receiver

ECE 491 Fall 2007Lecture 13 - More Data Comm.6 Receiver Design - General Approach  Clock receiver at a fixed multiple of data rate (16x)  Use falling edge of start bit to synchronize and then  Delay to middle of start bit and check (ignore “spurious” start bits)  Delay to middle of each data bit and sample  Delay to middle of stop bit and check (framing error if stop bit ≠ 1)

ECE 491 Fall 2007Lecture 13 - More Data Comm.7 Receiver Design - General Approach  Use shift register to convert serial - parallel  Use counters to calculate delay values  Use a Finite State Machine as control unit

ECE 491 Fall 2007Lecture 13 - More Data Comm.8 Coding Data for Clock Recovery  Start bit / Stop bit works OK for short data packets (e.g., bytes)  Alternative approach: embed clock in transmitted signal and re-generate with clock recovery 10MHz clock +/- 100ppm Flip- Flop Flip- Flop Sender Sender’s Clock Flip- Flop Clock Recovery Unit 10MHz clock +/- 100ppm Receiver Network Link Elasticity buffer Graphic Source: N. McKeown, cs244a Lecture Notes, Stanford University, Winter 2007

ECE 491 Fall 2007Lecture 13 - More Data Comm.9 Some Common Transmission Codes NRZ NRZI RZ BPRZ Manchester

ECE 491 Fall 2007Lecture 13 - More Data Comm.10 NRZ - Non-Return to Zero NRZ  Each cell contains 0 or 1 for entire length  Simple and reliable for short-distances  Requires separate clock or embedded signals for synchronization or a digital phase-lock loop  Can’t recover clock for long strings of 0 or 1  Won’t work in transition-sensitive media cell

ECE 491 Fall 2007Lecture 13 - More Data Comm.11 NRZI - Non-Return to Zero Invert-on-1s  Inverts signal each time a cell contains a “1”  Phase-Locked Loop (PLL) can recover clock as long as a long string of “0”s isn’t present  Example application: magnetic tape cell NRZI

ECE 491 Fall 2007Lecture 13 - More Data Comm.12 RZ - Return to Zero  Transmits value for only half the bit period  PLL can recover clock as long as a long string of “0”s isn’t present cell RZ

ECE 491 Fall 2007Lecture 13 - More Data Comm.13 BPRZ - Bipolar Return to Zero  Like RZ, but “1”s alternatively transmitted as positive or negative to make it DC-balanced  PLL can recover clock as long as a long string of “0”s isn’t present  Used in telephone system T1 links with zero suppression cell BPRZ

ECE 491 Fall 2007Lecture 13 - More Data Comm.14 Manchester Code  Guaranteed at least one transition in each cell  DC-balanced  PLL can always recover clock!  Used in Ethernet cell Manchester

ECE 491 Fall 2007Lecture 13 - More Data Comm.15 Frequency Spectrum for 10Mb/s Ethernet 10MHz5MHz freq Magnitude NRZ coding Manchester coding 5MHz Allows PLL-based clock recovery Graphic Source: N. McKeown, cs244a Lecture Notes, Stanford University, Winter 2007 No DC frequency component!

ECE 491 Fall 2007Lecture 13 - More Data Comm.16 Approaches to Clock Recovery  Use a PLL (common in high-speed networks)  Use a sequential circuit with one-shots (e.g., original Ethernet)  Use a multiple of the transmission clock (e.g., 16X) and synchronize on each bit transition

ECE 491 Fall 2007Lecture 13 - More Data Comm.17 Looking Ahead: Ethernet  Data encoded in packets using Manchester Code  Each packet starts with a preamble which allows receiver to synchronize clock recovery  Start frame delimiter (SFD) indicates start of packet data  Arbitary-length data frame follows SFD preamble SFD data

ECE 491 Fall 2007Lecture 13 - More Data Comm.18 Coming Up  Synchronizing interacting FSMs: Handshaking  Manchester Transmitter & Receiver