5/7/2007VTS'071 Delay Test Quality Evaluation Using Bounded Gate Delays Soumitra Bose Intel Corporation, Design Technology, Folsom, CA 95630 Vishwani D.

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Presentation transcript:

5/7/2007VTS'071 Delay Test Quality Evaluation Using Bounded Gate Delays Soumitra Bose Intel Corporation, Design Technology, Folsom, CA Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn, AL 36849

5/7/2007VTS'072 Problem Statement Investigate logic simulation with bounded delays specified for process variation. Improve upon existing min-max delay simulation.

5/7/2007VTS'073 Some Previous Work J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, “System Simulation with MIDAS,” AT&T Tech. Jour., vol. 70, no. 1, pp , January A. K. Pramanick and S. M. Reddy, “On the Fault Coverage of Gate Delay Fault Detecting Tests,” IEEE Trans. CAD, vol. 16, no. 1, pp , January S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-max Timing Analysis and Application to Asynchronous Circuits,” Proc. IEEE, vol. 87, no. 2, pp , February 1999.

5/7/2007VTS'074 Digital Circuit Timing and Delay Test Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized with clock

5/7/2007VTS'075 C17: Zero-Delay Simulation CK Robustly tested path Non-robustly tested path Untested path

5/7/2007VTS'076 C17: Min-Max Delay Simulation , /f max Performance range Nominal delay = 3.5 (min,max) delay = 3,4

5/7/2007VTS'077 Min-Max Delay Simulation 11 4,6 1,4 2,2 0,0 1, f max Range of operation 0

5/7/2007VTS'078 Improving Min-Max Delay Simulation 11 4,6 1,4 2,2 0,0 1, Fall at time x Output rises at least 2 units after the later of inputs falls. Ghost hazard 1 x x+2 6 x f max

5/7/2007VTS'079 A New Idea in Simulation Generate ambiguity intervals at fanouts. Propagate ambiguity interval lists through gates – similar to fault lists in concurrent fault simulation. Use ambiguity interval correlations among reconverging signals to improve hazard analysis.

5/7/2007VTS'0710 Sketch of New Simulation Algorithm An event generated at a fanout node generates an ambiguity list entry consisting of: Originating fanout signal name Ambiguity interval, initially (0,0) Gate evaluation: Examine multiple events with same originating signal Overlapping ambiguity periods: analyze interference Non-overlapping ambiguity periods: propagate independently Ambiguity list propagation: If an event propagates through a gate, the corresponding ambiguity list is propagated to output with ambiguity interval adjusted for (min,max) gate delays.

5/7/2007VTS'0711 Benchmark Circuits Zero-delay path simulation 5-20 thousand random vectors Delay model: –Nominal delay of each gate = 3.5 units –Min-max delay (3, 4), i.e., ±14% variation f max = 1/(nominal delay of critical path) Min-max delay simulation: re-determine f max

5/7/2007VTS'0712 Path Delay Coverage Circuit Faults ×10 6 Vectors ×10 3 Non-rob. detection CPU s P4 Linux WS c c c c c c c c × c

5/7/2007VTS'0713 Critical Path Delay and f max time Primary input event Primary output event on non-robust critical path Nominal delay of critical path 1/f max time 1/f’ max Delay range Percent change in f max = 100 (f max – f’ max ) / f max Min-max delay simulation: Zero-delay path simulation: Min-max performance range

5/7/2007VTS'0714 Determination of f max Circuit Zero-delay path fault simulation Hazard-list min-max sim. (last ambiguity interval) f max change % Nominal delay Maximum delay Begin End c c – 14.3 c c – 16.5 c – 0.46 c – 13.7 c – 19.6 c c – 7.5

5/7/2007VTS'0715 Conclusion Delay independent simulation becomes too pessimistic when we want the result to remain correct in the presence of large process variations. Conventional min-max delay (bounded delay) simulation produces extra ambiguity periods (hazards) because correlations between signals are neglected. Pessimism (ambiguity, hazards) is reduced when correlation among reconverging signals is considered. This paper presents an improved min-max delay (bounded delay) simulation algorithm.