טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Final A Presentation Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

Memory System for Micro Satellite Problems In Space Short time “ Bit Flips ” Permanent malfunction – “ Latch Ups ” Memory is especially vulnerable to these kind of failures !

Memory System for Micro Satellite Block Diagram of Conventional Memory System Generator Memory Bus Memory Controller

Memory System for Micro Satellite Block Diagram of a Memory System Using 3 Memory Controllers Upon a Bus Generator Bus Memory Controller 1 Memory Controller 2 Memory Controller 3 Memory

Memory System for Micro Satellite Single EDAC Based Memory System (using TMR) EDA C Generator Bus Memory Controller 1 Memory Controller 2 Memory Controller 3 Memory TMR

Memory System for Micro Satellite Optimal Memory System Generator Bus Opt Memory Module 1 Opt Memory Module 2 Opt Memory Module 3 Memory TMR

Memory System for Micro Satellite Demands From Memory Module Transparency to user Modularity Provide Reliability (use of EDAC) As fast as possible Minimizing implementation failures – using “ black boxes ”

Memory System for Micro Satellite EDAC Connection Between SDRAM Controller and Memory Memory Module PLB IPIF Bus Memory SDRAM Controller IPIC Code EDAC Parity Memory

Memory System for Micro Satellite EDAC Connection Between SDRAM Controller and PLB IPIF Memory Module PLB IPIF Bus Memory SDRAM Controller IPIC EDAC

Memory System for Micro Satellite Optimal Memory Module Optimal Memory Module PLB IPIF Bus Memory SDRAM Controller 1 IPIC Code EDAC Parity Memory SDRAM Controller 2

Memory System for Micro Satellite Theoretical & Actual Performance Theoretical max BW of SDRAM is 400 MB/Sec: SDRAM operating frequency : 100 MHz 32 bits of data = 4B Refresh Period = 4096 cycles Actual SDRAM performance: SDRAM transaction time = 4 + 1*BL [cycles]  BL := Burst Length in SDRAM Transaction Efficiency factor (EF) = BL/(4+BL) Actual frequency = EF*100Mhz

Memory System for Micro Satellite BW for up to 32bit transactions with single read/write is 80 MB/Sec: 32 bits of data = 4B = 1[BL] => EF = 0.2 => Actual Frequency = 20Mhz BW for single PLB transaction (64 bit) is 132 MB/Sec: 64 bits of data = 8B = 2[BL] => EF = 0.33 => Actual Frequency = 33Mhz  SDRAM handles 32bit (4B) in each cycle BW for up to 32bit transactions with single read/write is 80 MB/Sec: 32 bits of data = 4B = 1[BL] => EF = 0.2 => Actual Frequency = 20Mhz BW for single PLB transaction (64 bit) is 132 MB/Sec: 64 bits of data = 8B = 2[BL] => EF = 0.33 => Actual Frequency = 33Mhz  SDRAM handles 32bit (4B) in each cycle

Memory System for Micro Satellite Reliability vs. Delay EDAC unit adds E delay cycles TMR unit adds R delay cycles Rewriting data = Memory Module Time (MMT) = EDAC + SDRAM = E BL

Memory System for Micro Satellite Hardware Constraints SDRAM memory chip  Data width : 16 bit = 2B TMR simulation will multiply each SDRAM transaction and each EDAC rewrite 3 times (for each memory module)

Memory System for Micro Satellite Reliable Memory System Performance (without hardware constraints) T = TMR + SDRAM transaction + rewrite + rewrite = R + (3)(MMT) = R + (3)( E BL) [cycles] EF = BL/[R + (3)(E+4+BL)] EDAC TMR

Memory System for Micro Satellite Reliable Memory System Performance (with hardware constraints) T = TMR + (3)SDRAM transactions + (3)rewrites + (3)rewrites = R + (9)(MMT) = R + (9)( E BL) [cycles] EF = BL/[R + (9)(E+4+BL)] EDAC TMR

Memory System for Micro Satellite Reliable Memory System Performance – No Error Occurs T = TMR + SDRAM transaction = R + MMT = R + E BL [cycles] EF = BL/[R + (E+4+BL)]

Memory System for Micro Satellite Example Let ’ s review a system with smallest delays:  E = 1 cycle  R = 1 cycle BW for single PLB transaction (64 bit) 64 bits of data = 8B = 4[BL]  Reliable system with hardware constraints: EF = => Actual Frequency = 4.9Mhz => BW = 9.8MB/s  Reliable system without hardware constraints: EF = => Actual Frequency = 14.3Mhz => BW = 28.6MB/s  SDRAM handles 16bit (2B) in each cycle

Memory System for Micro Satellite Example - continue  Reliable system (no error occurs): EF = 0.4 => Actual Frequency = 40Mhz => BW = 80MB/s  Conventional system:  comparing with 32bit data width SDRAM (no parity) EF = => Actual Frequency = 33.33Mhz => BW = 132MB/s

Memory System for Micro Satellite Optimal Memory System (under test) Generator Bus Opt Memory Module 1 Opt Memory Module 2 Opt Memory Module 3 Memory TMR Corruption Unit

Memory System for Micro Satellite Completed Tasks Study the Virtex-II Pro component design. Study the PPC405 Processor core Study the VHDL development environment and VHDL. Writing a tester hardware of the LED ’ s – from VHDL design through synthesis, and place&route using Xillinx EDK. Midterm

Memory System for Micro Satellite Completed Tasks (continue) Writing a tester software with use of UART capabilities (Telnet). Building up a standard computer system and writing an application to test its memory. Design architecture of reliable memory system and internal memory modules Final

Memory System for Micro Satellite Second Semester Goals Study the probability model of error in a memory system in space. Implementation of the designed memory system.  Connect module to IPIF  Implement the optimal memory module.  Implement the optimal memory system. System testing  Debug.  Implement a memory corruption unit. System integration of the memory system in a complete computer system.