Chapter 1 Computer Abstractions and Technology

Chapter 1 — Computer Abstractions and Technology — 2 The Computer Revolution Progress in computer technology Underpinned by Moore’s Law Makes novel applications feasible Computers in automobiles Cell phones Human genome project World Wide Web Search Engines Computers are pervasive §1.1 Introduction

Chapter 1 — Computer Abstractions and Technology — 3 Classes of Computers Desktop computers General purpose, variety of software Subject to cost/performance tradeoff Server computers Network based High capacity, performance, reliability Range from small servers to building sized Embedded computers Hidden as components of systems Stringent power/performance/cost constraints

Chapter 1 — Computer Abstractions and Technology — 4 The Processor Market An average USA Family (2006): 12 gadgets 3 TVs, 2 PCs, others (game consoles, MP3 players, cell phones, etc.)

Computers in Cars Chapter 1 — Computer Abstractions and Technology — 5 First car with a computer: 1978 Cadillac Seville “Trip Computer,” (modified 6802 microprocessor) Today’s average cars: 5~50 microprocessors Today’s luxury cars: BMW 7-series; Mercedes Benz S-class ~100 microprocessors umns/significantbits/ ?_requestid= computer.htm

Chapter 1 — Computer Abstractions and Technology — 6 What You Will Learn How programs are translated into the machine language And how the hardware executes them The hardware/software interface What determines program performance And how it can be improved How hardware designers improve performance What is parallel processing

Chapter 1 — Computer Abstractions and Technology — 7 Understanding Performance Algorithm Determines number of operations executed Programming language, compiler, architecture Determine number of machine instructions executed per operation Processor and memory system Determine how fast instructions are executed I/O system (including OS) Determines how fast I/O operations are executed

Chapter 1 — Computer Abstractions and Technology — 8 Below Your Program Application software Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Managing memory and storage Scheduling tasks & sharing resources Hardware Processor, memory, I/O controllers §1.2 Below Your Program

Chapter 1 — Computer Abstractions and Technology — 9 Levels of Program Code High-level language Level of abstraction closer to problem domain Provides for productivity and portability Assembly language Textual representation of instructions Hardware representation Binary digits (bits) Encoded instructions and data

10  2004 Morgan Kaufmann Publishers Five classic components of a computer Keyboard, mouse, joystick Instruction decode Control signals ALU, Registers Monitor Primary memory Cache Secondary memory

Chapter 1 — Computer Abstractions and Technology — 11 Components of a Computer Same components for all kinds of computer Desktop, server, embedded Input/output includes User-interface devices Display, keyboard, mouse Storage devices Hard disk, CD/DVD, flash Network adapters For communicating with other computers §1.3 Under the Covers The BIG Picture

Chapter 1 — Computer Abstractions and Technology — 12 Anatomy of a Computer Output device Input device Network cable

Chapter 1 — Computer Abstractions and Technology — 13 Anatomy of a Mouse Optical mouse LED illuminates desktop Small low-res camera Basic image processor Looks for x, y movement Buttons & wheel Supersedes roller-ball mechanical mouse

Chapter 1 — Computer Abstractions and Technology — 14 Through the Looking Glass LCD screen: picture elements (pixels) Mirrors content of frame buffer memory

Chapter 1 — Computer Abstractions and Technology — 15 Opening the Box

Chapter 1 — Computer Abstractions and Technology — 16 Inside the Processor (CPU) Datapath: performs operations on data Control: sequences datapath, memory,... Cache memory Small fast SRAM memory for immediate access to data

Chapter 1 — Computer Abstractions and Technology — 17 Inside the Processor AMD Barcelona: 4 processor cores

Chapter 1 — Computer Abstractions and Technology — 18 Abstractions Abstraction helps us deal with complexity Hide lower-level detail Instruction set architecture (ISA) The hardware/software interface Application binary interface The ISA plus system software interface Implementation The details underlying and interface The BIG Picture

Chapter 1 — Computer Abstractions and Technology — 19 A Safe Place for Data Volatile main memory Loses instructions and data when power off Non-volatile secondary memory Magnetic disk Flash memory Optical disk (CDROM, DVD)

Chapter 1 — Computer Abstractions and Technology — 20 Networks Communication and resource sharing Local area network (LAN): Ethernet Within a building Wide area network (WAN: the Internet Wireless network: WiFi, Bluetooth

Chapter 1 — Computer Abstractions and Technology — 21 Technology Trends Electronics technology continues to evolve Increased capacity and performance Reduced cost YearTechnologyRelative performance/cost 1951Vacuum tube1 1965Transistor Integrated circuit (IC) Very large scale IC (VLSI)2,400, Ultra large scale IC6,200,000,000 DRAM capacity

Chapter 1 — Computer Abstractions and Technology — 22 Defining Performance Which airplane has the best performance? §1.4 Performance

Chapter 1 — Computer Abstractions and Technology — 23 Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/… per hour How are response time and throughput affected by Replacing the processor with a faster version? Adding more processors? We’ll focus on response time for now…

Chapter 1 — Computer Abstractions and Technology — 24 Relative Performance Define Performance = 1/Execution Time “X is n time faster than Y” Example: time taken to run a program 10s on A, 15s on B Execution Time B / Execution Time A = 15s / 10s = 1.5 So A is 1.5 times faster than B

Chapter 1 — Computer Abstractions and Technology — 25 Measuring Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs’ shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance

Chapter 1 — Computer Abstractions and Technology — 26 CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = 250×10 –12 s Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = 4.0×10 9 Hz

Chapter 1 — Computer Abstractions and Technology — 27 CPU Time Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count

Chapter 1 — Computer Abstractions and Technology — 28 CPU Time Example Computer A: 2GHz clock, 10s CPU time Designing Computer B Aim for 6s CPU time Can do faster clock, but causes 1.2 × clock cycles How fast must Computer B clock be?

Chapter 1 — Computer Abstractions and Technology — 29 Instruction Count and CPI Instruction Count for a program Determined by program, ISA and compiler Average cycles per instruction Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix

Chapter 1 — Computer Abstractions and Technology — 30 CPI Example Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much? A is faster… …by this much

Chapter 1 — Computer Abstractions and Technology — 31 CPI in More Detail If different instruction classes take different numbers of cycles Weighted average CPI Relative frequency

Chapter 1 — Computer Abstractions and Technology — 32 CPI Example Alternative compiled code sequences using instructions in classes A, B, C ClassABC CPI for class123 IC in sequence 1212 IC in sequence 2411 Sequence 1: IC = 5 Clock Cycles = 2×1 + 1×2 + 2×3 = 10 Avg. CPI = 10/5 = 2.0 Sequence 2: IC = 6 Clock Cycles = 4×1 + 1×2 + 1×3 = 9 Avg. CPI = 9/6 = 1.5

Chapter 1 — Computer Abstractions and Technology — 33 Performance Summary Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c The BIG Picture

Chapter 1 — Computer Abstractions and Technology — 34 Power Trends In CMOS IC technology §1.5 The Power Wall ×1000 ×30 5V → 1V

Chapter 1 — Computer Abstractions and Technology — 35 Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction The power wall We can’t reduce voltage further We can’t remove more heat How else can we improve performance?

Chapter 1 — Computer Abstractions and Technology — 36 Uniprocessor Performance §1.6 The Sea Change: The Switch to Multiprocessors Constrained by power, instruction-level parallelism, memory latency

Chapter 1 — Computer Abstractions and Technology — 37 Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization

Chapter 1 — Computer Abstractions and Technology — 38 Manufacturing ICs Yield: proportion of working dies per wafer §1.7 Real Stuff: The AMD Opteron X4

Chapter 1 — Computer Abstractions and Technology — 39 AMD Opteron X2 Wafer X2: 300mm wafer, 117 chips, 90nm technology X4: 45nm technology

Chapter 1 — Computer Abstractions and Technology — 40 Integrated Circuit Cost Nonlinear relation to area and defect rate Wafer cost and area are fixed Defect rate determined by manufacturing process Die area determined by architecture and circuit design

Chapter 1 — Computer Abstractions and Technology — 41 SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, … SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point)

Chapter 1 — Computer Abstractions and Technology — 42 CINT2006 for Opteron X NameDescriptionIC×10 9 CPITc (ns)Exec timeRef timeSPECratio perlInterpreted string processing2, , bzip2Block-sorting compression2, , gccGNU C Compiler1, , mcfCombinatorial optimization ,3459, goGo game (AI)1, , hmmerSearch gene sequence2, , sjengChess game (AI)2, , libquantumQuantum computer simulation1, ,04720, h264avcVideo compression3, , omnetppDiscrete event simulation , astarGames/path finding1, , xalancbmkXML parsing1, ,1436, Geometric mean11.7 High cache miss rates

Chapter 1 — Computer Abstractions and Technology — 43 SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec)

Chapter 1 — Computer Abstractions and Technology — 44 SPECpower_ssj2008 for X4 Target Load %Performance (ssj_ops/sec)Average Power (Watts) 100%231, %211, %185, %163, %140, %118, %920, %70, %47, %23, %0141 Overall sum1,283,5902,605 ∑ssj_ops/ ∑power493

Chapter 1 — Computer Abstractions and Technology — 45 Pitfall: Amdahl’s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance §1.8 Fallacies and Pitfalls Can’t be done! Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5× overall? Corollary: make the common case fast

Chapter 1 — Computer Abstractions and Technology — 46 Fallacy: Low Power at Idle Look back at X4 power benchmark At 100% load: 295W At 50% load: 246W (83%) At 10% load: 180W (61%) Google data center Mostly operates at 10% – 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load

Chapter 1 — Computer Abstractions and Technology — 47 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn’t account for Differences in ISAs between computers Differences in complexity between instructions CPI varies between programs on a given CPU

Historical Perspective ENIAC built in World War II was the first general purpose computer Used for computing artillery firing tables 80 feet long by 8.5 feet high and several feet wide Each of the twenty 10 digit registers was 2 feet long Used 18,000 vacuum tubes Performed 1900 additions per second –Since then: Moore’s Law: transistor capacity doubles every months

CS152 / Kubiatowicz Lec1.49 8/29/01©UCB Fall 2001 °Primary Personal Computer Hardware Block Diagram Components in the PC shown above: Mother board PC components: CPU, Math Co-processor, SRAM cache, DRAM, Video RAM, BIOS ROM, PCI Bridge Peripherals: Monitor, Keyboard, Mouse, EISA Hard Drive, Floppy Disk, CD ROM, printer, scanner, USB drive Recent intel architectures incorporate a 3-chip chipset, consisting of - CPU - Central Processing Unit Northbridge - Connects CPU with DRAM, S-RAM cache, video RAM and Southbridge °Southbridge - Connects peripherals to the Northbridge chip Source: Chipset manufacturers: VIA, SiS

CS152 / Kubiatowicz Lec1.50 8/29/01©UCB Fall 2001 Computers in the News: Sony Playstation 2000 °(as reported in Microprocessor Report, Vol 13, No. 5) Emotion Engine: 6.2 GFLOPS, 75 million polygons per second Graphics Synthesizer: 2.4 Billion pixels per second Claim: Toy Story realism brought to games!

CS152 / Kubiatowicz Lec1.51 8/29/01©UCB Fall 2001 Microsoft XBOX360 architecture °CPU core 3 cores IBM 64bit PPC 90nm, 3.2GHz Performance : 115 GFLOPS °GPU core ATI R500 (Xeons) GPU 500MHz, 10MB embedded DRAM 48 ALU operations/cycle 500 million triangles/second 16 billion pixels/second at 4x MSAA

CS152 / Kubiatowicz Lec1.52 8/29/01©UCB Fall 2001 ATI R500 (XEONS) GPU architecture

CS152 / Kubiatowicz Lec1.53 8/29/01©UCB Fall 2001 Sony Play Station 3 – Cell architecture °Cell core 1 64-bit PPE control core 8 SPE arithmetic cores 90nm, 250 million transistors 4.06 GHz ~ 4.6GHz 256 GFLOPS °EIB Bus 78 ~ 197 GBps °PPE °The PPE consists of a POWER Processing Unit (PPU) connected to a 512KB L2 cache °The key design goals of the PPE are to maximize the performance/power ratio as well as the performance/area ratio. The PPU is a dual-issue, in- order processor with dual-thread support °SPE °consisting of a Synergistic Processing Unit (SPU) and a Memory Flow Controller (MFC). °SPU is a compute engine with SIMD support and 256KB of dedicated local storage. The MFC contains a DMA controller with an associated MMU, as well as an Atomic Unit to handle synchronization operations with other SPUs and the PPU

CS152 / Kubiatowicz Lec1.54 8/29/01©UCB Fall 2001 PPE architecture For instruction fetch, decode, branch, issue, and completion For all fixed-point instructions and all load/store-type instructions for all vector and floating-point instructions

CS152 / Kubiatowicz Lec1.55 8/29/01©UCB Fall 2001 SPE architecture Local memory stores instructions and data

Chapter 1 — Computer Abstractions and Technology — 56 Concluding Remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture The hardware/software interface Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance §1.9 Concluding Remarks