Marc Riedel Ph.D. Defense, Electrical Engineering, Caltech November 17, 2003 Combinational Circuits with Feedback

Combinational Circuits Logic GateBuilding Block:

Combinational Circuits Logic GateBuilding Block: feed-forward device

Combinational Circuits “AND” gate Common Gate:

Combinational Circuits “OR” gate Common Gate:

Combinational Circuits “XOR” gate Common Gate:

inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

Combinational Circuits inputsoutputs The current outputs depend only on the current inputs. combinational logic gate

Generally feed-forward (i.e., acyclic) structures. Combinational Circuits x y x y z z c s

Generally feed-forward (i.e., acyclic) structures. Combinational Circuits

Feedback How can we determine the output without knowing the current state?... feedback

Feedback How can we determine the output without knowing the current state?... ? ? ?

Example: outputs can be determined in spite of feedback. Feedback

0 0 Example: outputs can be determined in spite of feedback. Feedback

Example: outputs can be determined in spite of feedback. Feedback

Example: outputs can be determined in spite of feedback. Feedback

1 1 Example: outputs can be determined in spite of feedback. Feedback

There is feedback is a topological sense, but not in an electrical sense. Example: outputs can be determined in spite of feedback. Feedback

Admittedly, this circuit is useless... Example: outputs can be determined in spite of feedback. Feedback

Rivest’s Circuit Example due to Rivest:

0 0 Rivest’s Circuit

0 0 0 Example due to Rivest:

Rivest’s Circuit Example due to Rivest: 0 0 0

1 1 Rivest’s Circuit

1 1 1 Example due to Rivest: Rivest’s Circuit

Example due to Rivest: 1 1 Rivest’s Circuit 1

Example due to Rivest: 3 inputs, 6 fan-in two gates. 6 distinct functions, each dependent on all 3 variables. Addition: OR Multiplication: AND

Rivest’s Circuit Individually, each function requires 2 fan-in two gates:

An equivalent feed-forward circuit requires 7 fan-in two gates.

A feedback circuit with fewer gates than any equivalent feed-forward circuit. Rivest’s Circuit 3 inputs, 6 fan-in two gates. 6 distinct functions.

Rivest’s Circuit n inputs 2n fan-in two gates, 2n distinct functions.

... a Rivest’s Circuit gates An equivalent feed-forward circuit requires fan-in two gates.

Rivest’s Circuit n inputs 2n fan-in two gates, 2n distinct functions. A feedback circuit with the number of gates of any equivalent feed-forward circuit. 3 2

Prior Work Kautz first discussed the concept of feedback in logic circuits (1970). Huffman discussed feedback in threshold networks (1971). Rivest presented the first, and only viable, example of a combinational circuit with feedback (1977).

Prior Work F(X)F(X)G(X)G(X) e.g., add e.g., shift Stok discussed feedback at the level of functional units (1992). Malik (1994) and Shiple et al. (1996) proposed techniques for analysis. X G(F(X)) Y F(G(Y))

Questions 1.Is feedback more than a theoretical curiosity, even a general principle? Can we improve upon the bound of ? 3.Can we optimize real circuits with feedback?

Key Contributions 2.Efficient symbolic algorithm for analysis (both functional and timing). 1.A family of feedback circuits that are asymptotically the size of equivalent feed-forward circuits A general methodology for synthesis.

Ph.D. Defense Present examples with same property as Rivest’s circuits. Illustrate techniques for analysis. Focus on synthesis: methodology, examples, optimization results.

Example not symmetrical 4 inputs 8 gates 8 distinct functions

Examples, multiple cycles, 3 inputs9 gates, 9 distinct functions

Example, 5 inputs 20 gates, 20 distinct functions. (“stacked” Rivest circuits)

½ Example Generalization: family of feedback circuits ½ the size of equivalent feed-forward circuits. (sketch)

Analysis Functional analysis: determine if the circuit is combinational and if so, what values appear. Timing analysis: determine when the values appear. Contributions: 1.Symbolic algorithm based on Binary Decision Diagrams. 2.Optimizations based on topology (“first-cut” method).

Analysis Assume gates each have unit delay arrival times Explicit analysis:

Analysis Explicit analysis:

n inputs  combinations Exhaustive evaluation intractable. Analysis Explicit analysis:

Symbolic analysis: 0101 : 1212 : 0303 : 1414 : Analysis similarly for

Symbolic analysis: Analysis undefined evaluates to 1 evaluates to 0

Symbolic analysis: Analysis undefined evaluates to 1 evaluates to 0 range of values

Synthesis General methodology: optimize by introducing feedback in the substitution/minimization phase. Optimizations are significant and applicable to a wide range of circuits. Design a circuit to meet a specification.

Example: 7 Segment Display Inputs a b c d e f g Output xxxx

Example: 7 Segment Display a b c d e f g Output

Substitution/Minimization Basic minimization/restructuring operation: express a function in terms of other functions. Substitute b into a: (cost 9) a  ))(( xxxxxxxxx  (cost 8) Substitute c into a: (cost 5) Substitute c, d into a: (cost 4) a  )( bxxxxxbx  a  cxxcx 321  a  dccx  1

Substitution/Minimization Berkeley SIS Tool a  ))(( xxxxxxxxx  },,,{fdcb target function substitutional set a  dccx  1 low-cost expression   

Acyclic Substitution g f e b a c d Select an acyclic topological ordering: g f e d c b a       

g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  ))((dxxxxxx  )(cdxx  10 )( Select an acyclic topological ordering: Cost (literal count): 37 Acyclic Substitution e   3 cxb d ba  f

Select an acyclic topological ordering: Nodes at the top benefit little from substitution. g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  ))((dxxxxxx  )(cdxx  10 )( e   3 cxb d ba  f

Cyclic Substitution Try substituting every other function into each function: Not combinational! Cost (literal count): 30  0 1 ex dccx fba geex bcdx gxaxex egxxax      f g f d c b a       e 

Cost 30 Lower bound Cost 37 Upper bound Acyclic substitution Unordered substitution Cyclic solution? Cost 34

Cyclic Substitution g f e d c b a        Cost (literal count): 34 Combinational solution: xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f

Cyclic Substitution Cost (literal count): 34 Combinational solution: topological cycles g f e d c b a        xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f

Inputs x 3, x 2, x 1, x 0 Cost (literal count): 34 ba ga e e e c        1 no electrical cycles Cyclic Substitution g f e d c b a        xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f = [0,0,1,0]:

g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        Cyclic Substitution no electrical cycles xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

g f e d c b a        Cost (literal count): 34 ba ga e e e c        1        a b c d e f g Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,0,1,0]:

g f e d c b a        Cost (literal count): 34 Cyclic Substitution xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

g f e d c b a        Cost (literal count): 34 Cyclic Substitution ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: no electrical cycles

g f e d c b a        Cost (literal count): 34        Cyclic Substitution ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f no electrical cycles Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

g f e d c b a        Cost (literal count): 34 a b c d e f g Cyclic Substitution        ba a a 1 0 c        f xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]:

g f e d c b a        Cost (literal count): 34 Cyclic Substitution        ba a a 1 0 c        f a b d e f g xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx )(  cxxcx 301  xxxfx 1023 )(  f Inputs x 3, x 2, x 1, x 0 = [0,1,0,1]: c

Synthesis Strategy: Allow cycles in the substitution phase of logic synthesis. Find lowest-cost combinational solution )( )( )( xxxxxc xxxxxxb xxxxxxa       Collapsed: Cost: xxaxc cxxxxb xxbxa       Solution: Cost: 13

“Break-Down” approach Exclude edges Search performed outside space of combinational solutions cost 12 cost 13 cost 12 cost 13 combinational cost 14 Branch and Bound

“Build-Up” approach Include edges Search performed inside space of combinational solutions cost 17 cost 16 cost 15 not combinational cost 14 Branch and Bound cost 13 best solution

Implementation: CYCLIFY Program Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package). Trials on wide range of circuits –randomly generated –benchmarks –industrial designs. Consistently successful at finding superior cyclic solutions.

Benchmark Circuits Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify Circuit# Inputs# OutputsBerkeleySimplifyCaltechCyclifyImprovement dc % ex % p % t % bbsse % sse % 5xp % s % dk % apla % tms % cse % clip % m % s % t % ex % exp %

Benchmarks Example: EXP circuit Cyclic Solution (Caltech CYCLIFY ): cost 262 Acyclic Solution (Berkeley SIS ): cost 320 cost measured by the literal count in the substitute/minimize phase

Discussion A new definition for the term “combinational circuit”: a directed, possibly cyclic, collection of logic gates. Most circuits can be optimized with feedback. Optimizations are significant. Paradigm shift:

Current Work Implement more sophisticated search heuristics (e.g., simulated annealing). Extend ideas to a decomposition and technology mapping phases of synthesis. Address optimization of circuits for delay with feedback.

Future Directions inputsoutputs data structure  Structured Network Representations databases, biological systems,...

Binary Decision Diagrams Introduced by Lee (1959). Popularized by Bryant (1986). Graph-based Representation of Boolean Functions compact (functions of 50 variables) efficient (linear time manipluation) Widely used; has had a significant impact on the CAD industry

Binary Decision Diagrams x 2 x 3 x f 0 1 BDDs generally defined as Directed Acyclic Graphs Graph-based Representation of Boolean Functions

Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon

Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon **

Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon

Binary Decision Diagrams Short described a cyclic structure for a BDD variant (1960). We suggest cycles are a general phenomenon Future research awaits...