331 W02.1Spring 05 Announcements  HW1 is due on this Friday  Appendix A (on CD) is very helpful to HW1.

331 W02.2Spring 05 Review I: Execute Cycle  Q1: How does control know which instruction to fetch?  Q2: who does decode? What happens in decode phase?  Q3: How do control and datapath interact to finish exec phase?  Q4: What does datapath have? FetchDecodeExec

331 W02.3Spring 05 Review II: word length  What does 32-bit architecture mean?

331 W02.4Spring 05 Assembly Language  Language of the machine  More primitive than higher level languages e.g., no sophisticated control flow  Very restrictive e.g., MIPS arithmetic instructions  We’ll be working with the MIPS instruction set architecture l similar to other architectures developed since the 1980's l used by NEC, Nintendo, Silicon Graphics, Sony, … l 32-bit architecture -32 bit data line and address line -data and addresses are 32-bit

331 W02.5Spring 05 MIPS R3000 Instruction Set Architecture  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target  3 Instruction Formats: all 32 bits wide Registers Q: How many already familiar with MIPS ISA?

331 W02.6Spring 05 MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2  Those operands are contained in the datapath’s register file ( $t0, $s1,$s2 )  Operand order is fixed (destination first)

331 W02.7Spring 05 Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, d is stored in $s3 and the result is to be left in $s0, and $t0 is a temporary register, what is the assembler equivalent to the C statement h = (b - c) + d

331 W02.8Spring 05 Registers  Registers are l Faster than main memory l Can hold variables so that -code density improves (since registers are named with fewer bits than a memory location) – why is that?  Register addresses are indicated by using $

331 W02.9Spring 05 MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file l Holds thirty-two 32-bit registers -With two read ports and -One write port Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations

331 W02.10Spring 05 0$zero constant 0 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address

331 W02.11Spring 05 Registers vs. Memory  Arithmetic instructions operands must be registers, — only thirty-two registers provided  What about programs with lots of variables? l Store variables in the memory l Load variables from memory to registers before use; store them back to memory after use. Processor Control Datapath Memory Devices Input Output

331 W02.12Spring 05  MIPS has two basic data transfer instructions for accessing memory lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory  The data transfer instruction must specify l where in memory to read from (load) or write to (store) – memory address l where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register Accessing Memory

331 W02.13Spring 05  Memory is viewed as a large, single-dimension array, with an address  A memory address is an index into the array Processor – Memory Interconnections Processor Memory Addressable locations read addr/ write addr read data write data Q: what should be the smallest addressable unit?

331 W02.14Spring 05 MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

331 W02.15Spring 05 Byte Addresses  Since 8-bit bytes are so useful, most architectures address individual bytes in memory memory: 2 32 bytes = 2 30 words  Therefore, the memory address of a word must be a multiple of 4 (alignment restriction) Alignment restriction: requires that objects fall on address that is multiple of their size Aligned Not Aligned

331 W02.16Spring 05 Addressing Objects: Endianess and Alignment  Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA  Little Endian:rightmost byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msblsb little endian byte big endian byte 0

331 W02.17Spring 05 MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory DataWord Address $s3 holds 8

331 W02.18Spring 05 Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of integer array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 +4 $s3 +8 $s3 +12 $s3... A[2] A[3]... A[1] A[0]

331 W02.19Spring 05 Compiling with a Variable Array Index  Assuming A is an integer array whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b

331 W02.20Spring 05 MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+10 0) store word43sw $s1, 100($s2)Memory($s2+10 0) = $s1

331 W02.21Spring 05  Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18  Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct

331 W02.22Spring 05 MIPS Instruction Fields  op  rs  rt  rd  shamt  funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits

331 W02.23Spring 05  Consider the load-word and store-word instructions, l What would the regularity principle have us do? l New principle: Good design demands a compromise  Introduce a new type of instruction format l I-type for data transfer instructions l previous format was R-type for register  Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number

331 W02.24Spring 05 Memory Address Location  Example: lw $t0, 24($s2) Memory dataword address (hex) 0x x x x c 0xf f f f f f f f $s2 0x x $s2 = Note that the offset can be positive or negative

331 W02.25Spring 05  Example: sw $t0, 24($s2)  A 16-bit address means access is limited to memory locations within a region of  2 13 or 8,192 words (  2 15 or 32,768 bytes) of the address in the base register $s2 Machine Language - Store Instruction op rs rt 16 bit number

331 W02.26Spring 05 Assembling Code  Remember the assembler code we compiled for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS object code for these three instructions

331 W02.27Spring 05 Review: MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

331 W02.28Spring 05 Beyond Numbers  Most computers use 8-bit bytes to represent characters with the American Std Code for Info Interchange (ASCII)  So, we need instructions to move bytes around ASCIICharASCIICharASCIICharASCIICharASCIICharASCIIChar 133!49165A97a113q 234“50266B98b114r 335#51367C99c115s 4EOT36$52468D100d116t 537%53569E101e117u 6ACK38&54670F102f118v 739‘55771G103g119w 8bksp40(56872H104h120x 9tab41)57973I105i121y 10LF42*58:74J106j122z ;75K107k123{ 12FF44,60<76L108l124| 1547/63?79O111o127DEL

331 W02.29Spring 05 Loading and Storing Bytes  MIPS provides special instructions to move bytes lb$t0, 1($s3) #load byte from memory sb$t0, 6($s3) #store byte to memory  What 8 bits get loaded and stored? l load byte places the byte from memory in the rightmost 8 bits of the destination register -what happens to the other bits in the register? l store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory op rs rt 16 bit number

331 W02.30Spring 05 Example of Loading and Storing Bytes  Given following code sequence and memory state (contents are given in hexidecimal), what is the state of the memory after executing the code? add$s3, $zero, $zero lb$t0, 1($s3) sb$t0, 6($s3) Memory A 0 DataWord Address (Decimal) F F F F  What value is left in $t0?  What if the machine was little Endian?

331 W02.31Spring 05 Review: MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1 load byte32lb $s1, 101($s2)$s1 = Memory($s2+101) store byte40sb $s1, 101($s2)Memory($s2+101) = $s1

331 W02.32Spring 05 Review: MIPS R3000 ISA  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special  3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO OPrs rt rdshamtfunct OPrs rt 16 bit number OP 26 bit jump target Registers R format I format 6 bits5 bits 6 bits