March 16, 2009SSST'091 Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation Jins Davis Alexander Vishwani D. Agrawal Department of.

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Presentation transcript:

March 16, 2009SSST'091 Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation Jins Davis Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849

Objective Determine power dissipation in a digital CMOS circuit. March 16, 2009SSST'092

March 16, 2009SSST'093 Components of Power Dynamic – Signal transitions Logic activity Glitches – Short-circuit Static – Leakage P total =P dyn + P stat =P tran + P sc + P stat

March 16, 2009SSST'094 Power Per Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

March 16, 2009SSST'095 Number of Transitions

Problem Statement Problem - Estimate dynamic power consumed in a CMOS circuit for: – A set of input vectors – Delays subjected to process variation Challenge - Existing method, Monte Carlo simulation, is expensive. Find a lower cost solution. March 16, 2009SSST'096

Bounded (Min-Max) Delay Model March 16, 2009SSST'097 EA is the earliest arrival time LS is the latest stabilization time IV is the initial signal value FV is the final signal value IVFV LSEA IVFV EALS [d, D] EAdvLSdv EAsv=-∞LSsv=∞ EAsvLSsv EAdv=-∞LSdv=∞ Driving value Sensitizing value

Example March 16, 2009SSST'098 d D dD

Finding Number of Transitions March 16, 2009SSST'099 2, 2 1, EA LS 3 14 EA LS [0,4] [0,2] 6 17 EA LS [mintran,maxtran] where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

Estimating maxtran Nd: First upper bound is the largest number of transitions that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output values. N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further modify it as N = N – k where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs. The maximum number of transitions is lower of the two upper bounds: maxtran = min (Nd, N) March 16, 2009SSST'0910

First Upper Bound, Nd Nd = 1 + (LS – EA)/d └ ┘ March 16, 2009SSST'0911 d, D EA LS d

Examples of maxtran March 16, 2009SSST'0912 Nd = 1 + (18 – 3)/0 = ∞ N = = 8 maxtran=min (Nd, N) = 8 Nd = 1 + (23 – 6)/3 = 6 N = = 8 maxtran=min (Nd, N) = 6

Example: maxtran With Non-Zero k March 16, 2009SSST'0913 EAsv = - ∞ EAdv LSdv = ∞ LSsv EAsv = - ∞ LSdv = ∞ EAdvLSsv EALS [n1 = 6] [n2 = 4] [n1 + n2 – k = 8 ], where k = 2 [ 6 ] [ 4 ] [ – 2 = 8 ]

Simulation Methodology d, D = nominal delay ± Δ% Three linear-time passes for each input vector:  First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals.  Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays.  Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information. March 16, 2009 SSST'0914

15 Zero-Delay Vs. Event-Driven Simulation March 16, 2009SSST'09

Maximum Power Monte Carlo Simulation vs. Min-Max analysis for circuit C sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). March 16, 2009SSST'0916 R 2 is coefficient of determination, equals 1.0 for ideal fit.

Minimum Power March 16, 2009SSST'0917 R 2 is coefficient of determination, equals 1.0 for ideal fit.

Average Power R 2 is coefficient of determination, equals 1.0 for ideal fit. March 16, SSST'09

C880: Monte Carlo vs. Bounded Delay Analysis March 16, 2009SSST'0919 Monte Carlo SimulationBounded Delay Analysis Min Power (mW) Max Power (mW) CPU Time (secs) Min Power (mW) Max Power (mW) CPU Time (secs) Random Vectors, 1000 Sample Circuits

Power Estimation Results Circuits implemented using TSMC V CMOS library, with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. March 16, 2009SSST'0920

Conclusion Bounded delay model allows power estimation method with consideration of uncertainties in delays. Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. March 16, 2009SSST'0921