EECC722 - Shaaban #1 Lec # 2 Fall Simultaneous Multithreading (SMT) An evolutionary processor architecture originally introduced in 1995 by Dean Tullsen at the University of Washington that aims at reducing resource waste in wide issue processors. SMT has the potential of greatly enhancing superscalar processor computational capabilities by: –Exploiting thread-level parallelism (TLP), simultaneously issuing, executing and retiring instructions from different threads during the same cycle. –Providing multiple hardware contexts, hardware thread scheduling and context switching capability. –Providing effective long latency hiding.

EECC722 - Shaaban #2 Lec # 2 Fall SMT Issues SMT CPU performance gain potential. Modifications to Superscalar CPU architecture necessary to support SMT. SMT performance evaluation vs. Fine-grain multithreading, Superscalar, Chip Multiprocessors. Hardware techniques to improve SMT performance: –Optimal level one cache configuration for SMT. –SMT thread instruction fetch, issue policies. –Instruction recycling (reuse) of decoded instructions. Software techniques: –Compiler optimizations for SMT. –Software-directed register deallocation. –Operating system behavior and optimization. SMT support for fine-grain synchronization. SMT as a viable architecture for network processors. Current SMT implementation: Intel’s Hyper-Threading (2-way SMT) Microarchitecture and performance in compute-intensive workloads.

EECC722 - Shaaban #3 Lec # 2 Fall Microprocessor Architecture Trends CMPs SMT SMT/CMPs

EECC722 - Shaaban #4 Lec # 2 Fall Evolution of Microprocessors Source: John P. Chen, Intel Labs

EECC722 - Shaaban #5 Lec # 2 Fall Microprocessor Frequency Trend Result: Deeper Pipelines Longer stalls Higher CPI (lowers effective performance per cycle)  Frequency doubles each generation Ë Number of gates/clock reduce by 25%  Leads to deeper pipelines with more stages (e.g Intel Pentium 4E has 30+ pipeline stages) Realty Check: Clock frequency scaling is slowing down! (Did silicone finally hit the wall?) Pentium(R) Pentium Pro (R) Pentium(R) II MPC , S A A ,000 10, Mhz Gate Delays/ Clock Intel IBM Power PC DEC Gate delays/clock Processor freq scales by 2X per generation

EECC722 - Shaaban #6 Lec # 2 Fall Parallelism in Microprocessor VLSI Generations Simultaneous Multithreading SMT: e.g. Intel’s Hyper-threading Chip-Multiprocessors (CMPs) e.g IBM Power 4 Multiple micro-operations per cycle Chip-Level Parallel Processing (Superscalar)

EECC722 - Shaaban #7 Lec # 2 Fall CPU Architecture Evolution: Single Threaded/Issue Pipeline Traditional 5-stage integer pipeline. Increases Throughput: Ideal CPI = 1

EECC722 - Shaaban #8 Lec # 2 Fall CPU Architecture Evolution: Superscalar Architectures Fetch, issue, execute, etc. more than one instruction per cycle (CPI < 1). Limited by instruction-level parallelism (ILP).

EECC722 - Shaaban #9 Lec # 2 Fall Empty or wasted issue slots can be defined as either vertical waste or horizontal waste: –Vertical waste is introduced when the processor issues no instructions in a cycle. –Horizontal waste occurs when not all issue slots can be filled in a cycle. Superscalar Architectures: Issue Slot Waste Classification

EECC722 - Shaaban #10 Lec # 2 Fall Sources of Unused Issue Cycles in an 8-issue Superscalar Processor. Processor busy represents the utilized issue slots; all others represent wasted issue slots. 61% of the wasted cycles are vertical waste, the remainder are horizontal waste. Workload: SPEC92 benchmark suite. Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1 Average 1.5 instructions/cycle issue rate Single-Threaded

EECC722 - Shaaban #11 Lec # 2 Fall Single-Threaded Superscalar Architectures: All possible causes of wasted issue slots, and latency-hiding or latency reducing traditional techniques that can reduce the number of cycles wasted by each cause. Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1

EECC722 - Shaaban #12 Lec # 2 Fall Fine-grain or Traditional Multithreaded Processors Multiple HW contexts (PC, SP, and registers). Only one context or thread issues instructions each cycle. Performance limited by Instruction-Level Parallelism (ILP) within each individual thread: –Can reduce some of the vertical issue slot waste. –No reduction in horizontal issue slot waste. Example Architecture: The Tera Computer System Advanced CPU Architectures:

EECC722 - Shaaban #13 Lec # 2 Fall Fine-grain or Traditional Multithreaded Processors Fine-grain or Traditional Multithreaded Processors The Tera Computer System The Tera computer system is a shared memory multiprocessor that can accommodate up to 256 processors. Each Tera processor is fine-grain multithreaded: –Each processor can issue one 3-operation Long Instruction Word (LIW) every 3 ns cycle (333MHz) from among as many as 128 distinct instruction streams (hardware threads), thereby hiding up to 128 cycles (384 ns) of memory latency. –In addition, each stream can issue as many as eight memory references without waiting for earlier ones to finish, further augmenting the memory latency tolerance of the processor. –A stream implements a load/store architecture with three addressing modes and 31 general-purpose 64-bit registers. –The instructions are 64 bits wide and can contain three operations: a memory reference operation (M-unit operation or simply M-op for short), an arithmetic or logical operation (A-op), and a branch or simple arithmetic or logical operation (C-op). Source:

EECC722 - Shaaban #14 Lec # 2 Fall VLIW: Intel/HP VLIW: Intel/HP IA-64 Explicitly Parallel Instruction Computing (EPIC) Strengths: –Allows for a high level of instruction parallelism (ILP). –Takes a lot of the dependency analysis out of HW and places focus on smart compilers. Weakness: –Limited by instruction-level parallelism (ILP) in a single thread. –Keeping Functional Units (FUs) busy (control hazards). –Static FUs Scheduling limits performance gains. –Resulting overall performance heavily depends on compiler performance. Advanced CPU Architectures:

EECC722 - Shaaban #15 Lec # 2 Fall Single Chip Multiprocessor Strengths: –Create a single processor block and duplicate. –Exploits Thread-Level Parallelism. –Takes a lot of the dependency analysis out of HW and places focus on smart compilers. Weakness: –Performance within each processor still limited by individual thread performance (ILP). –High power requirements using current VLSI processes. Advanced CPU Architectures:

EECC722 - Shaaban #16 Lec # 2 Fall Advanced CPU Architectures: Single Chip Multiprocessor

EECC722 - Shaaban #17 Lec # 2 Fall SMT: Simultaneous Multithreading Multiple Hardware Contexts running at the same time (HW context: registers, PC, and SP etc.). Reduces both horizontal and vertical waste by having multiple threads keeping functional units busy during every cycle. Builds on top of current time-proven advancements in CPU design: superscalar, dynamic scheduling, hardware speculation, dynamic HW branch prediction, multiple levels of cache, hardware pre-fetching etc. Enabling Technology: VLSI logic density in the order of hundreds of millions of transistors/Chip. –Potential performance gain is much greater than the increase in chip area and power consumption needed to support SMT.

EECC722 - Shaaban #18 Lec # 2 Fall SMT With multiple threads running penalties from long-latency operations, cache misses, and branch mispredictions will be hidden: –Reduction of both horizontal and vertical waste and thus improved Instructions Issued Per Cycle (IPC) rate. Functional units are shared among all contexts during every cycle: –More complicated register read and writeback stages. More threads issuing to functional units results in higher resource utilization. CPU resources may have to resized to accommodate the additional demands of the multiple threads running. –(e.g cache, TLBs, branch prediction tables, rename registers)

EECC722 - Shaaban #19 Lec # 2 Fall SMT: Simultaneous Multithreading

EECC722 - Shaaban #20 Lec # 2 Fall The Power Of SMT Time (processor cycles) SuperscalarTraditional Multithreaded Simultaneous Multithreading Rows of squares represent instruction issue slots Box with number x: instruction issued from thread x Empty box: slot is wasted

EECC722 - Shaaban #21 Lec # 2 Fall SMT Performance Example InstCodeDescriptionFunctional unit ALUIR5,100R5 = 100Int ALU BFMULF1,F2,F3F1 = F2 x F3FP ALU CADDR4,R4,8R4 = R4 + 8Int ALU DMULR3,R4,R5R3 = R4 x R5Intmul/div ELWR6,R4R6 = (R4)Memory port FADDR1,R2,R3R1 = R2 + R3Int ALU GNOTR7,R7R7 = !R7Int ALU HFADDF4,F1,F2F4=F1 + F2FP ALU IXORR8,R1,R7R8 = R1 XOR R7Int ALU JSUBIR2,R1,4R2 = R1 – 4Int ALU KSWADDR,R2(ADDR) = R2Memory port 4 integer ALUs (1 cycle latency) 1 integer multiplier/divider (3 cycle latency) 3 memory ports (2 cycle latency, assume cache hit) 2 FP ALUs (5 cycle latency) Assume all functional units are fully-pipelined

EECC722 - Shaaban #22 Lec # 2 Fall SMT Performance Example (continued) 2 additional cycles for SMT to complete program 2 Throughput: –Superscalar: 11 inst/7 cycles = 1.57 IPC –SMT: 22 inst/9 cycles = 2.44 IPC –SMT is 2.44/1.57 = 1.55 times faster than superscalar for this example

EECC722 - Shaaban #23 Lec # 2 Fall Modifications to Superscalar CPUs Necessary to support SMT Multiple program counters and some mechanism by which one fetch unit selects one each cycle (thread instruction fetch policy). A separate return stack for each thread for predicting subroutine return destinations. Per-thread instruction retirement, instruction queue flush, and trap mechanisms. A thread id with each branch target buffer entry to avoid predicting phantom branches. A larger register file, to support logical registers for all threads plus additional registers for register renaming. (may require additional pipeline stages). A higher available main memory fetch bandwidth may be required. Larger data TLB with more entries to compensate for increased virtual to physical address translations. Improved cache to offset the cache performance degradation due to cache sharing among the threads and the resulting reduced locality. –e.g Private per-thread vs. shared L1 cache. Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2

EECC722 - Shaaban #24 Lec # 2 Fall Current Implementations of SMT Intel’s recent implementation of Hyper-Threading Technology (2-thread SMT) in its current P4 Xeon processor family represent the first and only current implementation of SMT in a commercial microprocessor. The Alpha EV8 (4-thread SMT) originally scheduled for production in 2001 is currently on indefinite hold :( Current technology has the potential for 4-8 simultaneous threads: –Based on transistor count and design complexity.

EECC722 - Shaaban #25 Lec # 2 Fall A Base SMT Hardware Architecture. Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2

EECC722 - Shaaban #26 Lec # 2 Fall Example SMT Vs. Superscalar Pipeline The pipeline of (a) a conventional superscalar processor and (b) that pipeline modified for an SMT processor, along with some implications of those pipelines. Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages Based on the Alpha SMT-2 Two extra pipeline stages added for reg. Read/write to account for the size increase of the register file

EECC722 - Shaaban #27 Lec # 2 Fall Intel Xeon Processor Pipeline Source: Intel Technology Journal, Volume 6, Number 1, February 2002.Intel Technology Journal SMT-8

EECC722 - Shaaban #28 Lec # 2 Fall Intel Xeon Out-of-order Execution Engine Detailed Pipeline Source: Intel Technology Journal, Volume 6, Number 1, February 2002.Intel Technology Journal SMT-8

EECC722 - Shaaban #29 Lec # 2 Fall SMT Performance Comparison Instruction throughput from simulations by Eggers et al. at The University of Washington, using both multiprogramming and parallel workloads: Multiprogramming workload Superscalar Traditional SMT Threads Multithreading Parallel Workload SuperscalarMP2MP4 Traditional SMT Threads Multithreading

EECC722 - Shaaban #30 Lec # 2 Fall The following machine models for a multithreaded CPU that can issue 8 instruction per cycle differ in how threads use issue slots and functional units: Fine-Grain Multithreading: –Only one thread issues instructions each cycle, but it can use the entire issue width of the processor. This hides all sources of vertical waste, but does not hide horizontal waste. SM:Full Simultaneous Issue. –This is a completely flexible simultaneous multithreaded superscalar: all eight threads compete for each of the 8 issue slots each cycle. This is the least realistic model in terms of hardware complexity, but provides insight into the potential for simultaneous multithreading. The following models each represent restrictions to this scheme that decrease hardware complexity. SM:Single Issue,SM:Dual Issue, and SM:Four Issue: –These three models limit the number of instructions each thread can issue, or have active in the scheduling window, each cycle. –For example, in a SM:Dual Issue processor, each thread can issue a maximum of 2 instructions per cycle; therefore, a minimum of 4 threads would be required to fill the 8 issue slots in one cycle. SM:Limited Connection. –Each hardware context is directly connected to exactly one of each type of functional unit. –For example, if the hardware supports eight threads and there are four integer units, each integer unit could receive instructions from exactly two threads. –The partitioning of functional units among threads is thus less dynamic than in the other models, but each functional unit is still shared (the critical factor in achieving high utilization). Possible Machine Models for an 8-way Multithreaded Processor Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1

EECC722 - Shaaban #31 Lec # 2 Fall Comparison of Multithreaded CPU Models Complexity A comparison of key hardware complexity features of the various models (H=high complexity). The comparison takes into account: –the number of ports needed for each register file, –the dependence checking for a single thread to issue multiple instructions, –the amount of forwarding logic, –and the difficulty of scheduling issued instructions onto functional units. Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1

EECC722 - Shaaban #32 Lec # 2 Fall Simultaneous Vs. Fine-Grain Multithreading Performance Instruction throughput as a function of the number of threads. (a)-(c) show the throughput by thread priority for particular models, and (d) shows the total throughput for all threads for each of the six machine models. The lowest segment of each bar is the contribution of the highest priority thread to the total throughput. Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1 Workload: SPEC92

EECC722 - Shaaban #33 Lec # 2 Fall Results for the multiprocessor MP vs. simultaneous multithreading SM comparisons.The multiprocessor always has one functional unit of each type per processor. In most cases the SM processor has the same total number of each FU type as the MP. Simultaneous Multithreading Vs. Single-Chip Multiprocessing Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1

EECC722 - Shaaban #34 Lec # 2 Fall Impact of Level 1 Cache Sharing on SMT Performance Results for the simulated cache configurations, shown relative to the throughput (instructions per cycle) of the 64s.64p The caches are specified as: [total I cache size in KB][private or shared].[D cache size][private or shared] For instance, 64p.64s has eight private 8 KB I caches and a shared 64 KB data Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al., Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages SMT-1 Best overall performance of configurations considered achieved by 64s.64s (64K data cache shared 64K instruction cache shared)

EECC722 - Shaaban #35 Lec # 2 Fall The Impact of Increased Multithreading on Some Low Level Metrics for Base SMT Architecture Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2

EECC722 - Shaaban #36 Lec # 2 Fall Possible SMT Thread Instruction Fetch Scheduling Policies Round Robin: –Instruction from Thread 1, then Thread 2, then Thread 3, etc. (eg RR 1.8 : each cycle one thread fetches up to eight instructions RR 2.4 each cycle two threads fetch up to four instructions each) BR-Count: –Give highest priority to those threads that are least likely to be on a wrong path by by counting branch instructions that are in the decode stage, the rename stage, and the instruction queues, favoring those with the fewest unresolved branches. MISS-Count: –Give priority to those threads that have the fewest outstanding Data cache misses. ICount: –Highest priority assigned to thread with the lowest number of instructions in static portion of pipeline (decode, rename, and the instruction queues). IQPOSN: –Give lowest priority to those threads with instructions closest to the head of either the integer or floating point instruction queues (the oldest instruction is at the head of the queue). Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2

EECC722 - Shaaban #37 Lec # 2 Fall Instruction Throughput For Round Robin Instruction Fetch Scheduling Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2 Best overall instruction throughput achieved using round robin RR.2.8 (in each cycle two threads each fetch a block of 8 instructions) Workload: SPEC92

EECC722 - Shaaban #38 Lec # 2 Fall Instruction throughput & Thread Fetch Policy Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2 Workload: SPEC92 All other fetch heuristics provide speedup over round robin Instruction Count ICOUNT.2.8 provides most improvement 5.3 instructions/cycle vs 2.5 for unmodified superscalar.

EECC722 - Shaaban #39 Lec # 2 Fall Low-Level Metrics For Round Robin 2.8, Icount 2.8 ICOUNT improves on the performance of Round Robin by 23% by reducing IQ clog by selecting a better mix of instructions to queue

EECC722 - Shaaban #40 Lec # 2 Fall Possible SMT Instruction Issue Policies OLDEST FIRST: Issue the oldest instructions (those deepest into the instruction queue, the default). OPT LAST and SPEC LAST: Issue optimistic and speculative instructions after all others have been issued. BRANCH FIRST: Issue branches as early as possible in order to identify mispredicted branches quickly. Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages SMT-2 Instruction issue bandwidth is not a bottleneck in SMT as shown above

EECC722 - Shaaban #41 Lec # 2 Fall RIT-CE SMT Project Goals Investigate performance gains from exploiting Thread- Level Parallelism (TLP) in addition to current Instruction- Level Parallelism (ILP) in processor design. Design and simulate an architecture incorporating Simultaneous Multithreading (SMT) including OS interaction (LINUX-based kernel?). Study operating system and compiler optimizations to improve SMT processor performance. Performance studies with various workloads using the simulator/OS/compiler: –Suitability for fine-grained parallel applications? –Effect on multimedia applications?

EECC722 - Shaaban #42 Lec # 2 Fall RIT-CE SMT Project Project Chart

EECC722 - Shaaban #43 Lec # 2 Fall Simulator RIT CE Execution-driven, performance simulator. Derived from Simple Scalar tool set. Simulates cache, branch prediction, five pipeline stages Flexible: –Configuration File controls cache size, buffer sizes, number of functional units. Cross compiler used to generate Simple Scalar assembly language. Binary utilities, compiler, and assembler available. Standard C library (libc) has been ported. Sim-SMT Simulator Limitations:Sim-SMT Simulator Limitations: –Does not keep precise exceptions. –System Call’s instructions not tracked. –Limited memory space: Four test programs’ memory spaces running on one simulator memory space Easy to run out of stack space

EECC722 - Shaaban #44 Lec # 2 Fall Simulator Memory Address Space

EECC722 - Shaaban #45 Lec # 2 Fall sim-SMT Simulation Runs & Results Test Programs used: –Newton interpolation. –Matrix Solver using LU decomposition. –Integer Test Program. –FP Test Program. Simulations of a single program –1,2, and 4 threads. System simulations involve a combination of all programs simultaneously –Several different combinations were run From simulation results: –Performance increase: Biggest increase occurs when changing from one to two threads. –Higher issue rate, functional unit utilization.

EECC722 - Shaaban #46 Lec # 2 Fall Performance (IPC) Simulation Results:

EECC722 - Shaaban #47 Lec # 2 Fall Simulation Results: Simulation Time

EECC722 - Shaaban #48 Lec # 2 Fall Instruction Issue Rate Simulation Results:

EECC722 - Shaaban #49 Lec # 2 Fall Performance Vs. Issue BW Simulation Results:

EECC722 - Shaaban #50 Lec # 2 Fall Functional Unit Utilization Simulation Results:

EECC722 - Shaaban #51 Lec # 2 Fall No Functional Unit Available Simulation Results:

EECC722 - Shaaban #52 Lec # 2 Fall Horizontal Waste Rate Simulation Results:

EECC722 - Shaaban #53 Lec # 2 Fall Vertical Waste Rate Simulation Results:

EECC722 - Shaaban #54 Lec # 2 Fall SMT: Simultaneous Multithreading Strengths: –Overcomes the limitations imposed by low single thread instruction-level parallelism. –Multiple threads running will hide individual control hazards (branch mispredictions). Weaknesses: –Additional stress placed on memory hierarchy Control unit complexity. –Sizing of resources (cache, branch prediction, TLBs etc.) –Accessing registers (32 integer + 32 FP for each HW context): Some designs devote two clock cycles for both register reads and register writes.