Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 4 MAD MAC th February, 2006 Gate Level Design W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan (revised & Updated) Schematic (adder)  To be done  Layout  Extraction, LVS, post-layout simulation

Multiply Add (MAD) / Multiply Accumulate Unit (MAC) Executes function AB+C on 16 bit floating point inputs Multiply and add in parallel to greatly speed up operation Rounding is only performed only once so greater accuracy than individual multiply and add functions. MAD MAC accelerates FP16 blending to enable true HDR graphics Bright things can be really bright Dark things can be really dark And the details can be seen in both Recap - MAD MAC 525

Design Decisions Using n pass shifters instead of regular gates for the muxes –Increases speed --- –Reduces transistor count –Reduces area –Complexity of the project remains the same

Block Diagram RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator Input Output 16

Updated Estimated Transistor Count n-pass gates Registers (I/O, pipelining,threading) Carry-Save Multiplier Carry-Select Adder/Subtractor Alignment Shifter Leading 0 Anticipator Normalize Rounding Exponents Total

Estimated area (in um sq) n-pass  Registers 9000  Multiplier  Adder  Align 3800  Leading zero counter 2500  Normalize 6500  Round 2000  Exponent calc 5000 Total 80300

Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Main Floorplan

Multiplier

And Array 726 transistors Full Adder Array 2640 transistors Input From Reg A 10 Input from Reg B Input To Adder 22

Schematics Multiplier: 11 x 11 Carry-Save Multiplier

Schematics Leading Zero Counter: Carry-Save Adder to count the leading zeroes of C

Schematics Align Exponents: N-pass shifter

Schematics I bit N-pass shifter used in the align block

Schematics Normalize: n-Pass Shifter to shift the result of the adder by the amount given by the Leading Zero Counter

Shifter for the Normalize

Schematics Round: Incrementer and Shifter

Pipeline Reg Critical Path RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Reg Y Leading 0 Anticipator Input 16

Questions?