ENEE 408C Lab Capstone Project: Digital System Design Verilog Tutorial Class Web Site:

Modules and Primitives Modules Modules The user-defined components module fulladder ( ) …endmodule Primitives Primitives Pre-defined components nand g( ) Have to specify inputs and outputs Can have multiple outputs Module instantiation fulladder f(<port_list); First port is output Have only one output Primitives instantiation nand g( );

Registers and Nets reg reg –stores 1 bit information by default –similar to C/C++ variables in syntax –used on both LHS and RHS in procedural assignment –cannot be used on LHS in continuous assignment wire wire –default width is 1 bit –establish connectivity between two components –driven by the components it connects to –used on LHS in continuous assignment –cannot be used on LHS in procedural assignment integer integer –a 32-bit reg

Port Declaration input input –must be wire type inout inout –must be wire type output output –can be reg or wire type If not specified, all of aboves are by default wire type. If not specified, all of aboves are by default wire type.

Behavioral Description VS. Structural Description Structural Description Structural Description –a Verilog description of schematic –easy to synthesize –like gate-level netlist –less readable from human’s point of view. Behavioral Description Behavioral Description –a description of the functionality –flexible and more readable –suitable for large scale design –not always synthesizable

Structure Description primitive instantiation (AND, NAND, OR, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOTIF) primitive instantiation (AND, NAND, OR, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOTIF) parameter value assignment parameter value assignment

Structural Description Example module weird_logic (a,b,c,d); output a; input b,c,d; wire w; nand g1(w,b,c); nor g2(a,w,d); endmodule primitive don’t forget

Behavioral Description 1 Boolean-Equation-Based Model Boolean-Equation-Based Model module weird_logic (a,b,c,d); output a; input b,c,d; wire w; assign w = ~(b & c); assign a = ~(w | d); endmodule –continuous assignment –level-sensitive –normally used for combinational circuits continuous assignment

Behavioral Description 2 Cyclic Behavior Model Cyclic Behavior Model module weird_logic (a,b,c,d); output a; input b,c,d; reg w,a; or c) w = ~(b & c); or posedge w) a = ~(w | d); endmodule –always block –can be both level and edge sensitive –do not expire after the last statements

Behavioral Description 2 Cyclic Behavior Model Cyclic Behavior Model module weird_logic (a,b,c,d); output a; input b,c,d; wire w; or c) w = ~(b & c); or posedge w) a = ~(w | d); endmodule –always block –can be both level and edge sensitive –do not expire after the last statements

Using Testbench By giving a set of combination of inputs to test the timing and functionality of your design. By giving a set of combination of inputs to test the timing and functionality of your design. Can be separate from your design. Can be separate from your design. Must match the interface of your design Must match the interface of your design Need not to be synthesizable. Need not to be synthesizable.

With Stimulus initial block initial block $monitor system task $monitor system task $time system task $time system task $display system task $display system task delay statements and assignments - discussion of simulator engine delay statements and assignments - discussion of simulator engine $finish system task $finish system task

Testbench Example module tb_weird_logic; wire A; reg B, C, D; weird_logic instance1(A, C, D, B); initial // two slashes introduce a single line comment begin $monitor ($time,,, "A = %b B = %b C = %b D = %b", A, B, C, D); //waveform for simulating the binaryToESeg driver //waveform for simulating the binaryToESeg driver #10 B = 0; C = 0; D = 0; #10 D = 1; #10 C = 1; D = 0; #10 $finish; endendmodule