Jan. 9, 2007 VLSI Design Conference Spectral RTL Test Generation for Microprocessors Nitin Yogi and Vishwani D. Agrawal Auburn University Department of ECE Auburn, AL 36849, USA

Jan. 9, 2007 VLSI Design Conference Outline Microprocessor testing Issues Problem and Approach RTL faults Spectral analysis & test generation Test set compaction RTL DFT Experimental Results Conclusion

Jan. 9, 2007 VLSI Design Conference Microprocessor Testing Issues Issues arising from Increased Design Complexity Increased Test Generation Complexity Viable Test Method: RTL test generation Advantages: Low testing complexity Early detection of testability issues Increased Demands on Testing Viable Test Method: Functional at-speed tests Advantages: Better defect coverage Detection of delay faults

Jan. 9, 2007 VLSI Design Conference Problem and Approach The problem is … Develop an RTL-based ATPG method to generate functional at-speed tests. And our approach is … Circuit characterization using RTL: RTL test generation Analysis of information content and noise in RTL vectors. Test generation for gate-level implementation: Generation of spectral vectors Fault simulation and vector compaction

Jan. 9, 2007 VLSI Design Conference Faults Modeled for an RTL Module Combinational Logic FF Inputs Outputs RTL stuck-at fault sites A circuit is an interconnect of several RTL modules.

Jan. 9, 2007 VLSI Design Conference Walsh Functions and Hadamard Spectrum H 8 = w0w0 w1w1 w2w2 w3w3 w4w4 w5w5 w6w6 w7w7 Walsh functions (order 8) Walsh functions form an orthogonal and complete set of basis functions that can represent any arbitrary bit-stream. Walsh functions are the rows of the Hadamard matrix. Example of Hadamard matrix of order 8:

Jan. 9, 2007 VLSI Design Conference Analyzing Bit-Streams 0 to -1 Bit-stream Vector 1 Vector 2. Input 1 Input 2. Bit-stream of Input 2

Jan. 9, 2007 VLSI Design Conference Spectral Characterization of a Bit-Stream Bit stream to analyze Correlating with Walsh functions by multiplying with Hadamard matrix. Essential component (others regarded noise) Hadamard Matrix Bit stream Spectral coeffs.

Jan. 9, 2007 VLSI Design Conference Generation of New Bit-Streams Perturbation Generation of new bit-stream by multiplying with Hadamard matrix Spectral components Essential component retained; noise components randomly perturbed New bit stream Bits changed Sign function -1 to 0

Jan. 9, 2007 VLSI Design Conference PARWAN Processor Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.

Jan. 9, 2007 VLSI Design Conference Power Spectrum for “Interrupt” Bit-Stream Spectral Coefficients Normalized Power Essential components Some noise components Random level (1/128) Analysis of 128 test vectors.

Jan. 9, 2007 VLSI Design Conference Power Spectrum for “DataIn[5]” Signal Theoretical random noise level (1/128) Normalized Power Spectral Coefficients Some essential components Some noise components Analysis of 128 test vectors.

Jan. 9, 2007 VLSI Design Conference Power Spectrum for Random Signal Normalized Power Theoretical random noise level (1/128) Spectral Coefficients Analysis of 128 random vectors.

Jan. 9, 2007 VLSI Design Conference Selecting Minimal Vector Sequences Using ILP Fault simulation of new sequences A set of perturbation vector sequences {V 1, V 2,.., V M } is generated. Vector sequences are simulated and all gate-level faults detected by each are obtained. Compaction problem Find minimum set of vector sequences that cover all detected faults. Minimize Count {V 1, …,V M } to obtain compressed seq. {V 1,…,V C }, where {V 1, …,V C } {V 1, …, V M }, and Fault Coverage {V 1, …,V C } = Fault Coverage {V 1, …,V M } Compaction problem is formulated as an Integer Linear Program (ILP) [1]. [1] P. Drineas and Y. Makris, “Independent Test Sequence Compaction through Integer Programming," Proc. ICCD’03, pp

Jan. 9, 2007 VLSI Design Conference RTL DFT Goals of DFT: Improve controllability and observability Most hard-to-detect faults were experimentally found to have poor observability XOR tree as DFT Low area overhead Low performance penalty Hard-to-detect RTL faults used for observation test points 10 observation test points selected Hard-to-detect RTL faults To test output XOR tree

Jan. 9, 2007 VLSI Design Conference Experimental Results No of RTL Faults No. of vectors CPU (s)RTL coverage (%) Gate-level fault coverage(%) %81.22% RTL characterization PARWAN processor

Jan. 9, 2007 VLSI Design Conference Experimental Results Gate-level Fault Coverage Circuit RTL Spectral ATPG* Gate-level ATPG* (FlexTest) Random vecs. Cov. (%) No. of vecs. CPU (secs) Cov. (%) No. of vecs. CPU (secs) Cov. (%) No. of vecs. Parwan98.23% % %2814 Parwan (with DFT) 98.77% % %2948 *Sun Ultra 5, 256MB RAM

Jan. 9, 2007 VLSI Design Conference Experimental Results

Jan. 9, 2007 VLSI Design Conference Experimental Results

Jan. 9, 2007 VLSI Design Conference Conclusion Spectral RTL ATPG technique applied to PARWAN processor. Proposed ATPG method provides: Good quality “almost” functional at-speed tests Lower test generation complexity Enables testability appraisal at RTL RTL based XOR tree as DFT was found to improve results. An alternative approach: Use functional vectors instead of RTL vectors. Yogi and Agrawal, “Spectral Characterization of Functional Vcetors for Gate-Level Fault Coverage Tests,” Proc. VDAT, August 2006

Jan. 9, 2007 VLSI Design Conference Thank You ! Questions ?