Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Reducing Voltage Supply Jins Davis Alexander.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Advertisements

Digital Integrated Circuits© Prentice Hall 1995 Low Power Design Low Power Design in CMOS.

2007 MURI Review The Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits Matthew J. Gadlage 1,2, Ronald.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

1 Authors: MILENA STANOJLOVIĆ PREDRAG PETKOVIĆ LABORATORY FOR ELECTRONIC DESIGN AUTOMATION Faculty of Electronic Engineering University of Nis.

Low Voltage Sequential Circuit With a Ring Oscillator Clock ELEC 6270 Low power design of Electronic Circuits Spring, 2009 Presented by Mridula Allani.

9/01/05ELEC / Lecture 41 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

A Tutorial on Battery Simulation - Matching Power Source to Electronic System Manish Kulkarni and Vishwani D. Agrawal Auburn University Auburn, AL 36849,

8/22/06 and 8/24/06 ELEC / Lecture 2 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Power.

REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy.

Nov. 29, 2005 ELEC Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project Presentation By Nitin Yogi.

Dec. 6, 2005ELEC Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university.

December 1, 2005 ELEC Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji.

4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION.

Dec. 6, 2005ELEC Class Presentation1 Reducing Switching Capacitance Using Buffers Brad Hill.

9/20/05ELEC / Lecture 81 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

IMPLEMENTATION OF µ - PROCESSOR DATA PATH

Nov. 29, 2005ELEC Power Minimization Using Voltage Reduction and Parallel Processing By Sudheer Vemula.

Lecture #24 Gates to circuits

POWER ANALYSIS Sai Siddharth Kumar Dantu ELEC7770 Advanced VLSI Design Team Project Advisor: Dr. V Agrawal.

Characterization of a CMOS cell library for low-voltage operation

ASIC vs. FPGA – A Comparisson Hardware-Software Codesign Voin Legourski.

11/29/2007ELEC Class Project Presentation1 LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department.

Fall 2006, Sep. 26, Oct. 3 ELEC / Lecture 7 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Dynamic Power:

1 32-bit parallel load register with clock gating ECE Department, 200 Broun Hall, Auburn University, Auburn, AL 36849, USA Lan Luo ELEC.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

8/23-25/05ELEC / Lecture 21 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Power-Aware Computing 101 CS 771 – Optimizing Compilers Fall 2005 – Lecture 22.

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

ECE 331 – Digital System Design Power Dissipation and Propagation Delay.

DC/DC Converter with Transparent Electronics for application on Photovoltaic Panels Romano Torres 19th July Supervisor: Vitor Grade Tavares Second.

Logic Optimization Mohammad Sharifkhani. Reading Textbook II, Chapters 5 and 6 (parts related to power and speed.) Following Papers: –Nose, Sakurai, 2000.

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

156 / MAPLD 2005 Rollins 1 Reducing Energy in FPGA Multipliers Through Glitch Reduction Nathan Rollins and Michael J. Wirthlin Department of Electrical.

ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.

ENGG 6090 Topic Review1 How to reduce the power dissipation? Switching Activity Switched Capacitance Voltage Scaling.

ICCAD 2003 Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level Yuvraj.

An Ultra Low Power DLL Design

32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS PRIYADHARSHINI S.

Conception d’un processeur DSP faible énergie en logique ternaire

Power Reduction for FPGA using Multiple Vdd/Vth

Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.

Low power AES implementations for RFID

A Class Presentation for VLSI Course by : Fatemeh Refan Based on the work Leakage Power Analysis and Comparison of Deep Submicron Logic Gates Geoff Merrett.

Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic.

MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit October 27th, 2005 AID–EMC: Low Emission Digital Circuit Design.

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

Using Cycle Efficiency as a System Designer Metric to Characterize an Embedded DSP and Compare Hard Core vs. Soft Core Advisor Dr. Vishwani D. Agrawal.

Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han Brian L. Evans Earl E. Swartzlander, Jr.

A Power Grid Analysis and Verification Tool Based on a Statistical Prediction Engine M.K. Tsiampas, D. Bountas, P. Merakos, N.E. Evmorfopoulos, S. Bantas.

A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design

XIAOYU HU AANCHAL GUPTA Multi Threshold Technique for High Speed and Low Power Consumption CMOS Circuits.

The dynamic behaviour of Resistive Plate Chambers

Comparative Efficiency Analysis of Dynamically Supplied Power Amplifiers (PA) Orlando Lazaro, Student Member, IEEE, and Gabriel A. Rincón-Mora, Senior.

Electrical Characteristics of IC’s Part 2

1 Very Low Voltage Operation of Benchmark Circuit c6288 Presented By: - Murali Dharan.

EE141 Project: 32x32 SRAM Abhinav Gupta, Glen Wong Optimization goals: Balance between area and performance Minimize area without sacrificing performance.

Low Power SRAM VLSI Final Presentation Stephen Durant Ryan Kruba Matt Restivo Voravit Vorapitat.

June 30th 2008Jacques Lefrancois1 CW base studies Last week June 24th at calo meeting : news that preliminary test done by Yuri Gilitski indicated that.

Dual-V DD Pass Transistor Logic Jeff Brantley and Sam Ridenour 1.

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

CERN PH MIC group P. Jarron 07 November 06 GIGATRACKER Meeting Gigatracker Front end based on ultra fast NINO circuit P. Jarron, G. Anelli, F. Anghinolfi,

STT-RAM Circuit Design

MICROPROCESSOR DESIGN1 IR/Inductive Drop Introduction One component of every chip is the network of wires used to distribute power from the input power.

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270.

Reading: Hambley Ch. 7; Rabaey et al. Sec. 5.2

Low Power and High Speed Multi Threshold Voltage Interface Circuits

ELEC 6970: Low Power Design Class Project By: Sachin Dhingra

Power Reduction Technique

Presentation transcript:

Nov. 29, 2005 ELEC Class Presentation 1 Reducing Voltage Supply Jins Davis Alexander

Nov. 29, 2005 ELEC Class Presentation 2 Objective… To reduce the power consumption by reducing VDD supply voltage and seeing its effect on power, delay and area. No effect on area.

Nov. 29, 2005 ELEC Class Presentation 3 What We Know…. Power Consumption is a quadratic function of Voltage. Decrease in supply Voltage increases the overall delay.

Nov. 29, 2005 ELEC Class Presentation 4 Power and Delay Power = CV DD 2 Delay= KV DD ─────── (V DD – V t ) α (from alpha-power model)

Nov. 29, 2005 ELEC Class Presentation 5 What I have done… Designed N*N array multiplier using VHDL. Used ELDO for power analysis and calculation of delay. First simulated basic cell and found delay of Sumout to be greater than Cout.

Nov. 29, 2005 ELEC Class Presentation 6 Forced pulse signals for all possible vectors at inputs A and B for a 4x4 multiplier. Compared signal A[0] with Sum[2N-2] to calculate the overall worst case delay.

Nov. 29, 2005 ELEC Class Presentation 7 Results of 4x4 array multiplier. VoltageAvg.Power (uW)Delay (ns)

Nov. 29, 2005 ELEC Class Presentation 8 % Results Voltage(% Decrease) Avg Power(% Decrease) Delay (% Increase) 16.7%37.5%10% 33.3%65.6%33% 44.4%79.5%127%

Nov. 29, 2005 ELEC Class Presentation 9 Dynamic Power vs. Voltage

Nov. 29, 2005 ELEC Class Presentation 10 Delay vs. Voltage

Nov. 29, 2005 ELEC Class Presentation 11 Static Power vs. Voltage

Nov. 29, 2005 ELEC Class Presentation 12 Conclusion. Reducing Voltage decrease power significantly. However at lower voltages the delay increase is very significant. Transistor sizing, parallel processing can help reduce the overall delay.

Nov. 29, 2005 ELEC Class Presentation 13 THANK YOU.