Threshold Voltage Assignment to Supply Voltage Islands in Core- based System-on-a-Chip Designs Milestone 1: Gall Gotfried Steven Beigelmacher 02/22/05

Overview Introduction Approach Direct Recursive Iterative Parquet Cost Function Milestones

Introduction Voltage islands are regions where nearby IP blocks may use a supply voltage different from the full-chip supply We propose taking voltage islands in a core- based SoC design, and adding Vth assignments and latency measures It looks a lot like a placement problem (simulated annealing, quadratic placement, etc)

Approach -- Direct Deterministic solution to block placement Integer Linear Programming Multiple equations solved Solution provides definite placement of blocks

Approach -- Recursive Bipartition large problem set into smaller definitive blocks Further partitioning of sub-blocks proceeds Apply solution to lowest level sub-blocks Reiterate up the hierarchy to reach overall solution Place smallest subsection of blocks first then combine to get placement of entire set of blocks

Approach -- Iterative A random placement of the blocks is initial With each iteration perturbations are made to the blocks Such perturbations include location, supply and threshold voltage changes An assessment is made between the new arrangement and previous

Parquet Block floorplanner program using iterative approach Simulated annealing Sequence pairs Places blocks according to nets Modify move function to place blocks according to Threshold voltages Least cost wiring delays

Cost Function Organize blocks with emphasis on Total area reduction Energy savings attributed to supply voltages and threshold voltages Wire length weights connecting different blocks Cost = W 1 (Energy contribution) + W 2 (Wire length) + W 3 (Area) + W 4 (1-Aspect Ratio) + W 5 (Negative Slack) W 1 + W 2 + W 3 + W 4 + W 5 = 1

Milestones Previous work exploration Begin implementing algorithm for Vdd island partitioning Deadline 02/23/2005 Extend Algorithm Test benchmarks on Vdd algorithm to attain similar results as paper suggests Begin extending algorithm to include optimum Vth assignment Deadline 03/21/2005 Achieve Results Test algorithm performance on benchmarks used in Vdd only algorithm Deadline 04/11/2005

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