Copyright  2006 Daniel D. Gajski 1 Extreme Makeover of System Design Science Daniel Gajski Center for Embedded Computer Systems (CECS) University of California,

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Presentation transcript:

Copyright  2006 Daniel D. Gajski 1 Extreme Makeover of System Design Science Daniel Gajski Center for Embedded Computer Systems (CECS) University of California, Irvine

Copyright  2006 Daniel D. Gajski 2 History of design flow Design Gap: HW, SW, Application Real gap: behavior and structure (semantics and syntax)

Copyright  2006 Daniel D. Gajski 3 Simulation based methodology Simuletable but not synthesizable or verifiable Ambiguous semantics of hardware/system level languages

Copyright  2006 Daniel D. Gajski 4 Arithmetic algebra Arithmetic algebra allows creation of expressions and equations

Copyright  2006 Daniel D. Gajski 5 Model algebra Model algebra allows creation of models and model equivalences

Copyright  2006 Daniel D. Gajski 6 Methodology based on model algebra Algebra := Model algebra := Refinement is an ordered set of model transformations if and only if model B = t m ( … ( t 2 ( t 1 ( model A ) ) ) … ) Design methodology := Question: { models }? ; { transformations }?

Copyright  2006 Daniel D. Gajski 7 Why Model Algebra? 1.Defines SL semantics 2.Defines SL languages and styles 3.Identifies SL methodology 4.Enables SL design automation 5. Closes SW-HW gap 6. Introduces interoperability 7. Supports IP trade

Copyright  2006 Daniel D. Gajski 8 Specify-Explore-Refine Methodology Design decisions Model refinement Replacement or re-composition

Copyright  2006 Daniel D. Gajski 9 Y-Chart

Copyright  2006 Daniel D. Gajski 10 Processor behavioral model Language C -> CDFG -> FSMD (FSM +DFG)

Copyright  2006 Daniel D. Gajski 11 Processor structure Programmable controller FU pipelining Datapath pipelining Data forwarding Configurable datapath Controller pipelining (Processor-level structural model: NISC)

Copyright  2006 Daniel D. Gajski 12 Processor synthesis Op1Op2 Op3 Op1Op2 S1 S2 S3 FSMD model Component selection CA scheduling Variable bindingOperation Binding Bus Binding Controller Synthesis Op2Op3 Op4 Op6 Op1 Op5 Processor

Copyright  2006 Daniel D. Gajski 13 System behavioral model (Serial-parallel processes: UML + C/ SystemC)

Copyright  2006 Daniel D. Gajski 14 System structure (Netlist of system components: processors, memories, buses)

Copyright  2006 Daniel D. Gajski 15 System Synthesis System behavior Proc Memory µProcessor Interface Comp. IP Bus Interface Custom HW System structure Profiling AllocationIF Synthesis Refinement Behavior BindingChannel Binding System Scheduling

Copyright  2006 Daniel D. Gajski 16 Does it work? Intuitively it does –Well defined models, rules, transformations, refinements –System level complexity simplified –Worked in the past: layout, logic, RTL? Proof of concept demonstrated –Embedded System Environment (ESE) –Automatic model generation –Model synthesis and verification –Universal IP: NISC –Productivity gains order of 1000 – What is next? –More contributions needed –Change of mind

Copyright  2006 Daniel D. Gajski 17 Conclusions Extreme makeover is necessary for a new paradigm, where –SW = HW = SOC = Embedded Systems –Simulation based chaos is not acceptable –Design methodology is based on scientific principles Model algebra is enabling technology for –Embedded system design –System methodology –CAD tools –Design science education Formalism introduces simplicity that allows –Automatic model generation (No need for languages) –Automatic synthesis and verification (No need for system designers) –Application driven system design (Application experts only needed)