331 Lec20.1Fall :332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

331 Lec20.2Fall 2003 Head’s Up  This week’s material l Basics of caches -Reading assignment – PH 7.2  Reminders

331 Lec20.3Fall 2003 Second Level Cache (SRAM) Review: A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed: 1 ns 2 ns 10 ns 50 ns 1,000 ns Size: 128 B 64 KB 256 KB 4 GB TB’s Cost: highest lowest  By taking advantage of the Principle of Locality: l Present the user with as much memory as is available in the cheapest technology at the access speed offered by the fastest technology.

331 Lec20.4Fall 2003 Review: Principle of Locality  Temporal Locality l Keep most recently accessed data items closer to the processor  Spatial Locality l Move blocks consisting of contiguous words to the upper levels  Hit Time << Miss Penalty l Hit: data appears in some block in the upper level (Blk X) -Hit Rate: the fraction of accesses found in the upper level -Hit Time: Time to access the upper level = RAM access time + Time to determine hit/miss l Miss: data needs to be retrieve from a lower level block (Blk Y) -Miss Rate = 1 - (Hit Rate) -Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block to the processor Lower Level Memory Upper Level Memory To Processor From Processor Blk X Blk Y  In general, Average Access Time: l = Hit Time + Miss Penalty x Miss Rate

331 Lec20.5Fall 2003 Review: How is the Hierarchy Managed?  registers memory l by compiler (programmer?)  cache main memory l by the hardware  main memory disks l by the hardware and operating system (virtual memory) l by the programmer (files)

331 Lec20.6Fall 2003  Two questions to answer (in hardware): l Q1: How do we know if a data item is in the cache? l Q2: If it is, how do we find it?  First method: l Direct mapped -For each item of data at the lower level, there is exactly one location in the cache where it might be (i.e., lots of items at the lower level share locations in the upper level) l Block size is one word of data l Mapping: (word address) modulo (# of words in the cache) Cache

331 Lec20.7Fall 2003 Caching: A Simple First Example Cache Main Memory Q2: How do we find it? Use low order 2 memory address bits to determine which cache block (i.e., modulo the number of blocks in the cache) TagData Q1: Is it there? Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache Valid

331 Lec20.8Fall 2003 Direct Mapped Cache  Consider the main memory reference string Mem(0) 00 Mem(1) 00 Mem(0) 00 Mem(1) 00 Mem(2) miss hit 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) Start with an empty cache - all blocks marked as not valid 00 Mem(1) 00 Mem(2) 00 Mem(3)

331 Lec20.9Fall 2003 Another Reference String Mapping  Now consider the main memory reference string l Ping pong effect due to conflict misses - two memory locations that map into the same cache block Start with an empty cache - all blocks marked as not valid miss 00 Mem(0) Mem(4) Mem(0) Mem(0) Mem(0) Mem(4) Mem(4) 0 00

331 Lec20.10Fall 2003 Sources of Cache Misses  Compulsory (cold start or process migration, first reference): first access to a block l “Cold” fact of life, not a whole lot you can do about it l If you are going to run “billions” of instruction, Compulsory Misses are insignificant  Conflict (collision): l Multiple memory locations mapped to the same cache location l Solution 1: increase cache size l Solution 2: increase associativity  Capacity: l Cache cannot contain all blocks accessed by the program l Solution: increase cache size

331 Lec20.11Fall 2003  One word/block, cache size = 1K words MIPS Direct Mapped Cache Example Hit 20Tag 10 Index DataIndexTagValid Byte offset 20 Data 32

331 Lec20.12Fall 2003 Cache Summary  The Principle of Locality: l Program likely to access a relatively small portion of the address space at any instant of time -Temporal Locality: Locality in Time -Spatial Locality: Locality in Space  Three Major Categories of Cache Misses: l Compulsory Misses: sad facts of life. Example: cold start misses l Conflict Misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! l Capacity Misses: increase cache size  Cache Design Space l total size, block size, associativity (replacement policy) l write-hit policy (write-through, write-back) l write-miss policy (write allocate, write buffers)

331 Lec20.13Fall 2003  The off-chip interconnect and memory architecture can affect overall system performance in dramatic ways. Memory Systems that Support Caches CPU Cache Memory bus One word wide organization (one word wide bus and one word wide memory)  Assume 1. 1 clock cycle (2 ns) to send the address clock cycles (50 ns) for DRAM cycle time, 8 clock cycles (16 ns) access time 3. 1 clock cycle (2ns) to return a word of data  Memory-Bus to Cache bandwidth number of bytes accessed from memory and transferred to cache/CPU per clock cycle 32-bit data & 32-bit addr per cycle on-chip

331 Lec20.14Fall 2003 One Word Wide Memory Organization CPU Cache Memory bus on-chip  If the block size is one word, then for a memory access due to a cache miss, the pipeline will have to stall the number of cycles required to return one data word from memory cycle to send address cycles to read DRAM cycle to return data total clock cycles miss penalty  Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock /27 = 0.148

331 Lec20.15Fall 2003 One Word Wide Memory Organization, con’t CPU Cache Memory bus on-chip  What if the block size is four words? cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty  Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 25 cycles 1 4 x 25 = (4 x 4)/102 = 0.157

331 Lec20.16Fall 2003 One Word Wide Memory Organization, con’t CPU Cache Memory bus on-chip  What if the block size is four words and if a fast page mode DRAM is used? cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty  Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 25 cycles 8 cycles *8 = (4 x 4)/51 = 0.314

331 Lec20.17Fall 2003 Interleaved Memory Organization  For a block size of four words cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty CPU Cache Memory bank 1 bus on-chip Memory bank 0 Memory bank 2 Memory bank 3  Number of bytes transferred per clock cycle (bandwidth) for a single miss is bytes per clock 25 cycles (4 x 4)/30 = =

331 Lec20.18Fall 2003 DRAM Memory System Summary  Its important to match the cache characteristics l caches access one block at a time (usually more than one word)  with the DRAM characteristics l use DRAMs that support fast multiple word accesses, preferably ones that match the block size of the cache  with the memory-bus characteristics l make sure the memory-bus can support the DRAM access rates and patterns l with the goal of increasing the Memory-Bus to Cache bandwidth