GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 1 Electronics, Data Acquisition & Flight Software Gunther Haller Stanford Linear Accelerator Center Stanford University Project Electronics Engineer

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 2 Electronics, Data Acquisition & Flight Software  Requirements  Technical Architecture Front-End Electronics Tower Electronics Modules L1 Trigger, Event-Builder, Processor Farm & SIU Flight Software Power Budget Custom Integrated Circuits Status & Issues  Organization  Schedule & Milestones  Budget  Summary Outline

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 3 High Level Requirements Flow-down from Level 2: LAT Instrument Performance Specifications and LAT Interface Performance Specifications –Command and messaging –Readout configuration and control –Triggering, event data acquisition from sub-systems, event building –On-board event reconstruction/event filtering –On-board science analysis: transients (GRB, AGN flares) –Live-time monitor –Stream data to spacecraft –Instrument health monitoring and exception handling –LAT power system control –Support for I&T –Requirements for electronics: reliability, parts specs, performance, ….

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 4 Architecture Front-End TEM CAL TKR TKR-CAL TEM 16 TKR-CAL TEM’s16 TKR-CAL TEM’s (Tower Electronics Modules) with TKR and CAL electronics ACD TEM with ACD electronicsACD TEM with ACD electronics Global L1 Trigger Event-Builder & Processor Farm Spacecraft Interface Unit Power Supply System House-Keeping (HSK) System (T’s, I’s, V’s) Global L1 Trigger Event- Builder & Processor Farm Space- craft Interface Tower ACD TEM CAL TKR TKR-CAL TEM CAL TKR TKR-CAL TEM to/from SC Control & Data Signals Trigger Signals #1 #15 #16 LAT Power System HSK System Note: the GLB L1 TRG will be packaged together with the ACD TEM -> ACD-TRG TEM

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 5 CAL, TKR & ACD are front-end sub-systems, similar in architecture Signals from sensors are amplified & shaped Trigger: analog signals are discriminated and combined in front-end logic Global Trigger returns trigger acknowledge signal Data: analog signals are digitized, buffered, & zero- suppressed (latter order depends on sub-system) Each sub-system has one analog and one digital full- custom ASIC (see later) Front-End Electronics Analog Proces- sing A/D Conver- sion Hit bits from other channels Sensor Discri- minator TRG Logic Trigger Primitives Zero- Suppres- sion Event Buffer Event Data Global TRG Acknowledge

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 6 Tower Electronics Module (TEM) TEM electronics supports one tower each Control:Control: –directs TEM and Front-End Electronics –handles time-stamp and event number Trigger: forms local trigger primitives (e.g. layer-OR’s) and transmits them to L1 Global Trigger system Buffers: buffer event fragments of sub-systems. All front-end data is stored zero-suppressed. Transmitter: transmits complete TEM events to Event ACD TEM functions same as TKR- CAL TEM TKR Buffer TKR/CAL Control TKR Control From System Control TRG Buffer CAL Buffer Front-End Electronics CAL Trans mitter TRG Event Data to Event Builder TRG Primitives to Global Trigger TEM Electronics Note: on ACD TEM, CAL & TKR are replaced by ACD

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 7 Global L1 Trigger System Input: –16 sets of TKR and CAL trigger primitives (one set from each tower) –1 set of ACD trigger primitives from ACD TEM –Additional trigger sources: control, random, prescalers –Trigger throttle signal from each TEM Decides whether to trigger LAT. Generates L1 Trigger Acknowledge (TACK) signal via Look-Up Table Output: –TACK and trigger type is transmitted to all TEM’s –TRG event data is buffered and sent to EB Consequence of TACK: Front-end data is transferred into event buffers Throttles TACK when no memory buffers are available for event data Monitors LAT deadtime L1 Trigger –Rate: ~10 KHz max (~5.5 KHz avg) –Dead-time after TACK: 20  sec (CAL) –Latency: 2  sec 16 sets of CAL/TKR Primitives TEM Primitives TRG Logic with LUT To all TEM’s TACK and TRG Type Global L1 Trigger 1 set of ACD Primitives Other TRG sources Dead-Time Monitor TRG Event Buffer To Event- Builder

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 8 Event Builder (EB) Tower event fragments are variable- length Fragments are asynchronously received into 17 EB TEM buffers When an event is complete the entire event is transmitted to one of the processors in the farm The target processor is determined on an event-by-event basis by the event header (event number & event type) and its entry in the EB Look-Up Table (LUT) Two architectural choices: –Single-box solution: one EB with n processors –Multi-box solution: multiple EB’s with 1-2 processors each –Decision depends on # of processors required –Also impacts amount of redundant electronics required TEM 1 Buffer TKR-CAL TEM 1 TEM 16 Buffer TEM 17 Buffer LUT & Logic to Processor 1 TKR-CAL TEM 16 ACD TEM Transmission of complete events to Processor n

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 9 Processor Farm & SC Interface Unit Processor Farm –Class of Processors: Power PC 603E or PPC 750 –Choice of GLAST custom board Commercial board Spacecraft Interface Unit –Processor board –Command interface to SC (MIL1553) –High-speed data interface to SC –Power supply interface to SC –Environmental monitoring interface to SC

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 10 Flight Software Dataflow Event filtering Command, Control and Configuration Data Monitoring –Integrity & Quality Housekeeping –Temperatures, currents, … Uplink –Behaviour scripting –Software reload, reconfiguration Autonomous Behaviour –Transient detection and alert –Orbit related configuration (e.g. SAA transit) Level 2 Filter From Event Builder LAT Processor Farm Level 3 Filter 32 Mb/s* SSR 300 kb/s Orbit Average Spacecraft (capacities) Down- link * Overcapacity for burst conditions 30 Hz Event Rate: Max. 10 KHz 2 KHz (~10 Kb/event)

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 11 Instrument Power

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 12 Application-Specific Integrated Circuits –Six full-custom ASICs in front-end systems –One or two digital ASICs in DAQ system –Analog: manual layout –Typical Digital: VHDL -> Simulation -> Synthesis -> Auto Place&Route -> Verification –Several iterations in schedule for each ASIC ASIC TypePrel. PrototypeFull Engineering Model Submission Institution TKR AnalogexistsMarch 2001UCSC (SLAC) TKR DigitalexistsApril 2001UCSC, SLAC CAL AnalogexistsMarch 2001NRL, SLAC CAL DigitalJun 2001Dec 2001NRL ACD AnalogSep 2001Jan 2002GSFC ACD DigitalOct 2001Jan 2002GSFC TEM Digital (tbr) Oct 2001Feb 2002SLAC, HEPL

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 13 Target ASIC Technology 0.5 um Agilent Bulk CMOS 0.25 um TSMC Bulk CMOS 0.25 um/0.5 um Peregrine Silicon-on-Sapphire Total Radiation Dose: all radiation insensitive to well above 10 Krad requirement Single-Event Latchup Requirement: LET of 8 MeV-cm 2 /mg –SOS: no latchup –Agilent: prel. measurements good up to LET of 70 –TSMC: no measurements yet but has epitaxial layer Single-Event Upset –Use SEU “hardened” latches for configuration registers LET: Linear Energy Threshold

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 14 Status Requirement & Conceptual Design documents in draft for –ACD, TKR & CAL Electronics –Trigger & Dataflow Electronics –Aux. Systems, Interfaces Prototypes for three of the ASICs exist Software level 2 filtering demonstrated: 50  sec/event for PPC603E, 100 MHz Software Coding Infrastructure developed Basic concepts demonstrated in beam-test early 2000 and for present balloon-flight electronics: –Sub-system control & data readout –Generation of CAL and TKR trigger primitives –Assembly of CAL & TKR event fragments on TEM Electronics for balloon-flight in commissioning stage

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 15 Issues Hardware –SEU/SEL performance of some of the ASIC processes (will be tested) Software: Level 3 filter algorithm and CPU-cycle requirements –Cascades into Number of processors Organization of event-builder/processors. Options are –Single-box solution with EB and all processors –Multi-box solution with multiple (parallel) EB’s Tower Processor and Processor Processor communication

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 16 Organization NRL SU-HEPL SU-SLAC NRL SU-HEPL SU-SLAC NRL CEA- DAPNIA INFN SU-SLAC GSFC NRL SU-HEPL SU-SLAC NRL SU-HEPL SU-SLAC

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 17 Schedule

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 18 Milestones Electronics & Data Acquisition (E&DAQ) Requirements Review03/27/01 Flight Software Requirements Review04/04/01 E&DAQ PDR06/20/01 Flight Software PDR06/13/01 LAT Instrument PDR08/06/01 Engineering Model 1 (EM1) System Test Complete03/15/02 E&DAQ CDR06/19/02 Flight Software CDR06/12/02 LAT Instrument CDR08/05/02 Engineering Model 2 (EM2; flight software & DAQ) System Test Complete05/10/03 Deliver Electronics Units for Calibration Unit05/10/03 Assemble/Test Qual Unit07/15/03 Assemble/Test last Flight Unit12/01/03

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 19 Interim Electronics Cost Estimate* (Escalated K$) *DOE/NASA funding.

GLAST LAT Project DOE/NASA Review of the GLAST/LAT Project, Feb , 2001 Gunther Haller 20 Summary Requirements and Conceptual Design documents well under way Principles of tower event assembly and trigger demonstrated in beam-test electronics Prototypes of several ASICs exist Software coding infrastructure developed Schedule: fully entered in PMCS up to lowest level (L7) Budget –All labor and material cost items entered in PMCS –Revised bottoms-up estimate of components in the next few months Balloon-flight electronics, DAQ & software in commissioning stage (based on electronics used in beam-test FY2000)