AMC – Adaptive Mirror Controller Project supervised by: Mony Orbach Project performed by: Koren Erez, Turgeman Tomer Project supervised by: Mony Orbach Project performed by: Koren Erez, Turgeman Tomer Project duration – 1 year

IntroductionIntroduction The project is a collaboration between the Physic ’ s Adaptive Optics Lab and HS DSL. The project is a collaboration between the Physic ’ s Adaptive Optics Lab and HS DSL. Developing a system that controls adaptive mirrors, by changing the voltage of their capacitors (up to 128 capacitors). Developing a system that controls adaptive mirrors, by changing the voltage of their capacitors (up to 128 capacitors).

The Optical System

Signals & Rates Input: A serial signal from the computer through a USB. A serial signal from the computer through a USB.Output: 128 outlines of analog signal (0-295V). 128 outlines of analog signal (0-295V).Rate: The system will update all 128 outputs in 1mSec. The system will update all 128 outputs in 1mSec.

External Flow Chart AMC Optical Device Adaptive Mirror USB

AMC MMC Internal Flow Chart USB Adaptive Mirror D/A FPGA USB Interface Amp.

The Operating Machine (OM) Implemented as FSM within the FPGA. Implemented as FSM within the FPGA. Main tasks: Main tasks: –Data flow controlling. –High Voltage Amplifiers power up/down sequence Controlling. –Carrying out a self test. –FPGA-PC communication through the USB module. Including a Watch Dog Timer (WDT) feature for a PC-FPGA synchronization. Including a Watch Dog Timer (WDT) feature for a PC-FPGA synchronization.

The Operating Machine (OM) DLP, FPGA Power Up HVAmp Power Up MAIN Self test HVAmp Power Down System Power Down DLP ready HVAmps are powered on OK/Error Massage RUN Byte All capacitors were charged/ WDTR Shutdown Byte/ Ext. shutdown Button USB cable disconnection USB cable connection RUN Self Test Byte Status Byte DLP to PC Transmi t EOT EOT = End Of Transmission WDTR = Watch Dog Timer Reset DLP = USB Module HVAmp = High Voltage Amplifier The Control Bytes are marks in green

Milestones – Wiring and initial checking – Wiring and initial checking – FSM writing in VHDL – FSM writing in VHDL – VHDL simulation – VHDL simulation – SW & HW integration – SW & HW integration – Driver & application writing – Driver & application writing – Final integration & testing – Final integration & testing – Final report – Final report.

HVAmp Power Up/Down Improper power up/down sequence can damage the HVAmps (High Voltage Amplifiers). Improper power up/down sequence can damage the HVAmps (High Voltage Amplifiers). Power up sequence: Power up sequence: Vpp(300V)  Vnn(-5.5V)  Vdd(6.5V) Power down sequence: Power down sequence: Vdd(6.5V)  Vnn(-5.5V)  Vpp(300V)

HVAmp Power Up/Down In order to control the Power up/down sequence, The system includes Latch, Switches & Relay. In order to control the Power up/down sequence, The system includes Latch, Switches & Relay. The switches and the relay responsible on the physical connection between the power supplies and the HVAmps. The switches and the relay responsible on the physical connection between the power supplies and the HVAmps. The power up/down control lines toggle the switches for the appropriate sequence. The power up/down control lines toggle the switches for the appropriate sequence. The Latch locks the state of the switches when the system finished power up. This allows a reduction of control lines. The Latch locks the state of the switches when the system finished power up. This allows a reduction of control lines.

HVAmp Power Up/Down DLP (USB) Cyclone FPGA Computer Adaptive Mirror HVAmp Bus Exchange Relay Transceiver Quad Voltage Output D/A Transceiver Switches Latch Power Up/Down Unit HVAmp Power Supply CLKEPCSResetComparator '1' External shutdown Button HVAmp

Cyclone FPGA Adaptive Mirror HVAmp Bus Exchange Relay Transceiver Switches Latch HVAmp Power SupplyExternal shutdown Button HVAmp HVAmp Power Up/Down

The FPGA waits for a Control Sequence from the PC. The FPGA waits for a Control Sequence from the PC. The Control Sequence composed of 3 bytes: The Control Sequence composed of 3 bytes: According to The Control Byte the FPGA shifts to the next state: According to The Control Byte the FPGA shifts to the next state: RUN Byte - updating all 128 outputs with the data received from the PC.RUN Byte - updating all 128 outputs with the data received from the PC. Self Test Byte - initiating a self test cycle.Self Test Byte - initiating a self test cycle. Shutdown Byte - Power Down the High Voltage Amplifiers.Shutdown Byte - Power Down the High Voltage Amplifiers. Status Byte - Status reporting to the PC.Status Byte - Status reporting to the PC. The Operating Machine- MAIN State 0xFF 0x00 Control Byte 0xFF 0x00 Control Byte Flag

Self Test The self test gives indication that: The self test gives indication that: –All components were powered up. –All components are working properly. –Proper data flow. The FPGA sends the test ’ s result to the PC by the DLP module. The FPGA sends the test ’ s result to the PC by the DLP module.

Self Test DLP (USB) Cyclone FPGA Computer Adaptive Mirror HVAmp Bus Exchange Relay Transceiver Quad Voltage Output D/A Transceiver Switches Latch HVAmp Power Supply CLKEPCSResetComparator '1' External shutdown Button HVAmp

Self Test DLP (USB) Cyclone FPGA Computer Adaptive Mirror HVAmp Bus Exchange Transceiver Quad Voltage Output D/A Transceiver Comparator '1' External shutdown Button HVAmp

Self Test – Comparators Scheme