SRAM A-Factors for Simple 6T SRAM Cell using Microprocessor Logic CMOS Process Technology Average A-Factor =

0.15, TSMC, VLSI , Toshiba, VLSI (0.13 poly), Motorola, VLSI00, embedded! 85 (or 162 using 0.13) 0.13, IBM, SOI, VLSI , IBM, bulk, VLSI , TSMC, VLSI , IBM, VLSI , IBM, ISSCC , UMC, IEDM , Samsung, VLSI , Fujitsu, VLSI , Motorola, VLSI F, Company, Reference A factor

Virtual Silicon libraries based on United Microelectronics (UMC) processes A-factors: 0.25  m, high-performance (10 tracks): 2-in NAND/NOR: 371 INV: 248 MUX2: 867 DFF:  m, high-performance (11 tracks), quoted max density = 93.5K gates/mm 2, translating to 10.7  m 2 /gate or 330F 2 : 2-in NAND/NOR: 377 INV: 251 MUX2: 878 DFF:  m, high-density (8 tracks), about 20% smaller than high-performance, quoted max density = 173K gates/mm 2, translating to 5.8  m 2 /gate or 258F 2. 2-in NAND/NOR: 307 INV: 205 MUX2: 717 DFF: 1638 If we assume contacted metal pitch = 2.5*F (e.g. MP =  m for 0.25  m), this gives ~60 MP 2 for 2- in NAND/NOR, which is inline with BACPAC calcs

Current recommendations: SRAM cell size = F 2 Std. Cell size = 375F 2 ?? SRAM overhead: use factor of 1.6 (60% overhead penalty) These areas don’t include any white-space consideration so the actual packing density should be lower