Spike Sorting Algorithm implemented on FPGA Elad Ilan Asaf Gal Sup: Alex Z

The Vision - Develop a NeuroChip, a brain implanted microchip, able to maintain real time and on line interface with the brain tissue and an external HW. Develop a NeuroChip, a brain implanted microchip, able to maintain real time and on line interface with the brain tissue and an external HW.

System Schema -

The problem - Raw recorded signal contains huge amount of data (magnitude of GB/sec) Raw recorded signal contains huge amount of data (magnitude of GB/sec) In order to make the system feasible, we need minimize the amount of data transmission between the neurochip and the external HW. In order to make the system feasible, we need minimize the amount of data transmission between the neurochip and the external HW. Solution : Do most of the data processing on the neurochip (detection + sorting) Solution : Do most of the data processing on the neurochip (detection + sorting)

Neurochip block diagram

Objective - To explore different possibilities for the architecture and implementation of the sorting block. By implementing the sorting algorithms on FPGA, we will be able to compare them by their performance, HW requirements, and output size/rate. A simulation environment for validation and testing of the algorithms will be set as a SW or HW blocks.

The sorting problem - PCA algorithm: PCA algorithm: High performance: ~10% error High performance: ~10% error Requires a lot of computations (involves big matrix products) Requires a lot of computations (involves big matrix products)

Real time algorithms - Basic idea: Basic idea: Run PCA algorithm off-line on a set of training data, and extract parameters for more simple algorithms.

Hard Decision - We choose a set of the best separating time points We choose a set of the best separating time points Each spike is sampled in those time points Each spike is sampled in those time points The spike vector is then compared to the threshold vec. The spike vector is then compared to the threshold vec. A decision is made A decision is made based on the mean value of the result

Hard Decision - Where: Cmp – comparator ∑ – summator DAC – digital/analog converter Where: Cmp – comparator ∑ – summator DAC – digital/analog converter Cmp Spike Separation line ∑ Cmp Control block Reg CL n 16 Time stamp Neuron ID Reg – register n – log 2 (sets) CL – combinatorial logic Reg – register n – log 2 (sets) CL – combinatorial logic

Soft Decision - Similar to HD, but we sum the sampling points before the comparison. Similar to HD, but we sum the sampling points before the comparison. The summation is done on two time windows The summation is done on two time windows

Soft Decision -

Simulation Schema -

Simulation environment User: User: This block will calculate the control parameters needed for the algorithm operation based on a predefined training data. Electrode + A/D STUB: Electrode + A/D STUB: This block will inject the raw data into the sorting unit as a serial data. The data will come from existing records of neuronal activity. Detector STUB: Detector STUB: This block will emulate the neurochip detection unit. Since we want to evaluate the sorting unit independently, we will assume an ideal detector. PCA simulator: PCA simulator: This block will run the best known PCA sorting algorithm on the same inputs as the tested unit. Its result will use as a reference to evaluate the unit performance. CMP: CMP: A comparator block, which will compute the error rate of the unit relative to the PCA algorithm (which have about 10% error rate itself)

Back up Foils