S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 14: Interconnects Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Transistors + Wires = Circuits Wires (interconnects) are as important as transistors –Speed –Power –Noise Alternating layers run orthogonally

S. Reda EN160 SP’07 How interconnects contribute to delay and power? Interconnects have resistance, capacitance (and inductance) Interconnects increase circuit delay: –The wire capacitance adds loading to each gate –Long wires have significant resistance that further contribute to the delay Interconnects increase dynamic power: –Because of the wire capacitance

S. Reda EN160 SP’07 Wire geometry Pitch = w + s Aspect ratio: AR = t/w –Old processes had AR << 1 –Modern processes have AR  2 Pack in many skinny wires

S. Reda EN160 SP’07 1. Wire Resistance ρ = resistivity (W*m) R  = sheet resistance (Ω/  ) –  is a dimensionless unit(!)

S. Reda EN160 SP’07 How does the kind of metal impact resistivity? Until 180 nm generation, most wires were aluminum Modern processes often use copper –Cu atoms diffuse into silicon and damage FETs –Must be surrounded by a diffusion barrier

S. Reda EN160 SP’07 Contact and via resistance Contacts and vias also have 2-20 Ω Use many contacts for lower R –Many small contacts for current crowding around periphery

S. Reda EN160 SP’07 2. Wire capacitance Wire has capacitance per unit length –To neighbors –To layers above and below C total = C top + C bot + 2C adj

S. Reda EN160 SP’07 Factors impacting the capacitance Parallel plate equation: C =  A/d –Wires are not parallel plates, but obey trends –Increasing area (W, t) increases capacitance –Increasing distance (s, h) decreases capacitance Dielectric constant –  = k  0  0 = 8.85 x F/cm k = 3.9 for SiO 2 Processes are starting to use low-k dielectrics –k  3 (or less) as dielectrics use air pockets

S. Reda EN160 SP’07 M2 capacitance data Typical wires have ~ 0.2 fF/mm –Compare to 2 fF/mm for gate capacitance) Polysilicon has lower C but high R –Use sparingly for very short wires between gates

S. Reda EN160 SP’07 Given R and C, how to calculate interconnect delay? Wires are a distributed system –Approximate with lumped element models 3-segment  -model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment  -model for Elmore delay

S. Reda EN160 SP’07 Interconnect delay: the lumped case 0V VmVm V out Upper bound on delays in RC trees [Pileggi’97]

S. Reda EN160 SP’07 Interconnect delay: ideal analysis tpd~0.38RC

S. Reda EN160 SP’07 Interconnect delay: distributed Elmore delay lumped overestimates delay r = resistance per unit length c = capacitance per unit length (ideally, modeling using diffusion equation; covered in class)

S. Reda EN160 SP’07 Delay calculations Assuming ideal wires: Realistic wire modeling:

S. Reda EN160 SP’07 Layer stack AMI 0.6  m process has 3 metal layers Modern processes use metal layers Example: Intel 180 nm process M1: thin, narrow (< 3 ) –High density cells M2-M4: thicker –For longer wires M5-M6: thickest –For V DD, GND, clk Why do you think different metal layers have different widths/thickness?