Joe Gebis Computer Science Division University of California, Berkeley IRAM CAD Status and Plan

Joe Gebis, IRAM Retreat, Winter Outline CAD paths: –Custom layout –Synthesized –Macros Tool status

Joe Gebis, IRAM Retreat, Winter Combining various sources Memory Bank 0 Memory Bank 2 Memory Bank 4 Memory Bank 6 Memory Bank 1 Memory Bank 3 Memory Bank 5 Memory Bank 7 Crossbar Vector Lane 3 Vector Lane 2 Vector Lane 1 Vector Lane 0 Scalar core I/O FPU CTL Custom Macros Synthesized (UCB logic) Synthesized (Ext. logic)

Joe Gebis, IRAM Retreat, Winter Synthesized logic From external sources: scalar core, FP datapath From UCB: vector control, FPU VCS simulation, debugging synopsys synthesis apollo, saturn place+route, layout and timing optimization timemill dynamic timing primetime static timing hercules design rules check

Joe Gebis, IRAM Retreat, Winter Custom logic Crossbar Vector integer unit, register file spice circuit design cadence layout hercules design rules check starex ideal netlist extraction starrc parasitics extraction spice timing timemill timing verilog functional verification

Joe Gebis, IRAM Retreat, Winter Macros, top-level routing DRAM, SRAM macros synthesized blocks custom layout macrosapollo block placement, top-level routing hercules design rules check

Joe Gebis, IRAM Retreat, Winter Additional scripts Tiling generating layout wires, labels post-layout fixup netlist formatting for simulation etc Formatting with perl scripts Layout manipulation with custom GDS library

Joe Gebis, IRAM Retreat, Winter Tools status All tools installed, licensed Currently being used: –vcs, synopsys, cadence, hercules, starex, starrc, spice Set up: –apollo, timemill To be set up: –saturn, primetime

Joe Gebis, IRAM Retreat, Winter Computing resources Cluster of machines behind a firewall –10 Tatung UltraSparc U60 clones (400 MHz, 2 GB) High-memory machine for large extractions –Sun Ultra-4 with 4 GB VCS can run on UCB Millennium cluster –Dozens of 4-way 600 MHz servers