Noise Canceling in 1-D Data: Presentation #10 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 4 th, 2005 Chip Level Layout 3 Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (98%) –Spice simulation (85%)

Current Floorplan

Layer Masks - Poly

Layer Masks - Metal 1

Layer Masks – Metal 2

Layer Masks – Metal 3

Layer Masks – Metal 4

The Chip Dimensions –Width = µ –Height = µ Area = µ² Transistor count = –NMOS: –PMOS: Density = trans/µ² Aspect ratio = 1: 1.21 (dimensions from previous floorplan: W: µ H: µ A: µ²)

Floating Point Adder 1

Floating Point Adder 2

Floating Point Adder 3

Questions?