1 Serial Decoder & Multiplexer Ryan Bruno Gly Cruz Frank Gurtovoy Christopher Plowman Advisor: Dr. David Parent May 11 (or 16), 2005

2 Agenda Abstract Introduction –Why a Serial Decoder/Multiplexer? –Potential Applications –Theory of Operation Calculations Cadence Details Summary of Results Cost Analysis Conclusions

3 Abstract Target spec –Simple DFF-Stabilized Decoder and Mux –200Mhz clock frequency –Within 400μm x 400μm area –Power density spec of 23W/cm 2 Actual –Simple DFF-Stabilized Decoder and Mux –200MHz clock frequency –Area of 316μm x 274μm –12.9 mW of Power for 14.9 W/cm 2

4 Introduction Serial Decoder/Multiplexer –Allows a “Master” to communicate with multiple “Slaves” using fewer pins than dedicating a Port Applications –Microcontroller-based systems –Consumer Products Theory –Address and Data share signal at different times. –Decoder selects the receiving slave –Mux chooses the transmitting slave

5 Master Packet Scheme

6 Sample Packet

7 Longest Path Calculations CELL WN Load WP Load Cg or Cin of load  phl  plh A NSNNSN NSPNSP CdnCdn CdpCdpRWNWP (cm) Fss  cm BUFF2 1.50E E E E E E- 03Output Buffer BUFF1 1.89E E E E E E E- 04Output Buffer Tenacious INV 1.76E E E E E E E- 04 Input Stabilization DEC_NAND 1.50E E E E E E E- 04Decoder DFF_DATA_N ORS 3.46E E E E E E E- 03Address Hold DFF_DATA_M XS 6.12E E E E E E E- 03Address Hold DFF_DATA_N ORM 1.41E E E E E E E- 03Address Hold DFF_DATA_M XM 3.20E E E E E E E- 04Address Hold MISO_NOR E E E E E E E- 03 Master In Multiplexer

8 Mux Path Calculations CELL WN Load WP Load Cg or Cin of load  phl  plh A NSNNSN NSPNSP CdnCdn CdpCdpRWNWP (cm) Fss  cm BUFF2 1.50E E E E E E-03Output Buffer BUFF1 1.89E E E E E E E-04Output Buffer MISO_NOR E E E E E E E-03 Master In Multiplexer MUX_NOR E E E E E E E-04 Master In Multiplexer MUX_NAND-4*2 1.34E E E E E E E-04 Master In Multiplexer MUX_NAND-4*8 3.55E E E E E E E-04 Master In Multiplexer

9 Clock Block Calculations CELL WN Load WP Load Cg or Cin of load  phl  plh A NSNNSN NSPNSP CdnCdn CdpCdpRWNWP (cm) Fss  cm MISO_NOR 2.80E E E E E E E- 03 Address Capture Logic DFF_CB_NORS 3.22E E E E E E E- 03Clock Block DFF_CB_MXS 3.51E E E E E E E- 03Clock Block DFF_CB_NORM 1.01E E E E E E E- 03Clock Block DFF_CB_MXM 3.36E E E E E E E- 04Clock Block CB_NAND2 3.98E E E E E E E- 04Clock Block

10 Schematic

11 Schematic

12 Layout

13 Verification

14 Verification

15 MOSI Simulation

16 MISO Simulation

17 Cost Analysis Time spent on each phase of project –Verifying Logic:4 weeks –Verifying timing: 1 long night –Layout:2 long nights –Post-Extracted Timing:2 long nights –LVS Success on First Run with No Errors:Priceless

18 Lessons Learned Flip-Flops require special attention Start Early Work Together Start Early Routing is good fun

19 Summary Our circuit is within spec. –Clock > 200MHz –316 x 274 μm 14.9 W/cm 2 Potential Improvements: –Stabilization D-Flip-Flops –Parity Check –Tri-state Buffer output

20 Improvements

21 Acknowledgements Thanks to Cadence Design Systems. Thanks to Professor David Parent for his support. Thanks to Morris Jones, for his State Machine intervention. Thanks to Dr. T’s MIST Lab. Thanks to the janitorial staff of SJSU. Thanks to Coca-Cola and Gordon Biersch. Thanks to Nick’s Pizza and the ghetto pizza place across from the Subway we used to go to before the one opened in the Student Union. Thanks to Microsoft, Bungie, and Halo 2.

22 Tenacious EE Strikes Again