[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Mon. Nov. 11 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Current Version

AU Update  Simulation Results  Issues/Concerns  Huge Bus line leads to high parasitics  Error did not come up in schematic  Going to require a Huge Buffer (~4-8 um inverters)  Better solutions exist, but time constraints  Output Has semi-weak output that is correct  Assumes strong Bus line  Require Buffer at end to smooth out  ExtractedRC still broken for me, have to have someone else do extracted for me, just inconvenient

Layout

Output of Input load(2.16 um inverters)

Output of Input Load(4.18 um inverters)

11bits Counter Entering of car Clk

Entering of car Clk bit Counter: The layout is a little different from 11 bit counter. But the result is correct.

Shift Register Clk One of inputs SEL: Choose arm0 or arm1 Falling Edge Rising Edge

2:1 MUX x 110 Enable : Choose arm0 or arm1 some of outputs 10 bus (11bits) inputs from arm0 assumes it all equal to 0 10 bus (11bits) inputs from arm1 assumes it all equal to 1 When Enable signal oscillates, the outputs will oscillates with enable also.

16:1 MUX SEL2 SEL3 SEL0 SEL1 SEL3 ~ SEL0 : 0000~ 1111 Input [0:15] = [ ] ; Output

2:1 mux (8bit) IN1 = all 1 IN0 = all 0 IN1 IN0 SEL Out

8 bit Comparator IN0 IN1 OUT IN1 = 0 >> 1.8 >> 0 IN0 = all 0

Control for DEMUX If SEL0~SEL3 = [0010], we expect the OUT will be High. OUT

Control as trigger for Register INPUTS from ALUOther Outputs Targeted Register Output If SEL0~SEL3 = [0010], we expect the OUT will be HIGH and the second register will store all values from ALU

Light Control FSM  After running electrical simulations with extracted RC, a few glitches are found on waveforms.  Spent lot of on fixing it. Still can’t eliminate all of them but reduce them somewhat.

Light Control FSM Some glitches appear on these waveforms. Must fix the waveform for COMPLETE since it’s quite important for Tom’s FSM.

Light Control FSM Modified schematics. A bunch of buffers are used for fixing glitches.

Light Control FSM Modified layout. Quite similar to previous version since I allocated these buffers in the space within this FSM. Buffers for outputs Buffers for fixing glitches

Light Control FSM The glitches on COMPLETE signal are fixed. Others are improved. If the clock cycle is 1 second, these glitches are only about second in width.

Issue  Is that required to use more area and buffers to eliminate these glitches?  Basically people’s eyes wouldn’t be capable of noticing these.

Tom’s FSM  Much cleaner layout  Strict wire directionality  Better organization  More modular  Can’t get simulations to work  The new layout will make any changes easy to make (if the simulations don’t pass)  Simulating by tonight

Tom’s new FSM layout

Question ?