CS Fall 2005 – Lecture #29: Recap - 1 What we HOPE you learned in CS 150 … zLanguage of logic design yLogic optimization, state, timing, CAD tools zConcept of state in digital systems yAnalogous to variables and program counters in software systems zHardware system building yDatapath + control = digital systems zHardware system design methodology yHardware description languages: Verilog yTools to simulate design behavior: output = function (inputs) yLogic compilers synthesize hardware blocks of our designs yMapping onto programmable hardware (code generation) zContrast with software design yBoth map specifications to physical devices yBoth must be flawless…the price we pay for using discrete math

CS Fall 2005 – Lecture #29: Recap - 2 Current state of digital design zChanges in industrial practice yLarger designs yShorter time to market yCheaper products zScale yPervasive use of computer-aided design tools over hand methods yMultiple levels of design representation zTime yEmphasis on abstract design representations yProgrammable rather than fixed function components yAutomatic synthesis techniques yImportance of sound design methodologies zCost yHigher levels of integration yUse of simulation to debug designs

CS Fall 2005 – Lecture #29: Recap - 3 New ability: to accomplish the logic design task with the aid of computer-aided design tools and map a problem description into an implementation with programmable logic devices after validation via simulation and understanding of the advantages/disadvantages as compared to a software implementation CS 150: concepts/skills/abilities zBasics of logic design (concepts) zSound design methodologies (concepts) zModern specification methods (concepts) zFamiliarity with full set of CAD tools (skills) zAppreciation for differences and similarities (abilities) in hardware and software design

CS Fall 2005 – Lecture #29: Recap - 4 Representation of digital designs zPhysical devices (transistors, relays) zSwitches zTruth tables zBoolean algebra zGates zWaveforms zFinite state behavior zRegister-transfer behavior zConcurrent abstract specifications Simulation & Chipscope Verilog Structural & Behaviorial Descriptions

CS Fall 2005 – Lecture #29: Recap - 5 Digital System Design zDoor combination lock: ypunch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset yinputs: sequence of input values, reset youtputs: door open/close ymemory: must remember combination or always have it available as an input

CS Fall 2005 – Lecture #29: Recap - 6 Implementation in software integer combination_lock ( ) { integer v1, v2, v3; integer error = 0; static integer c[3] = 3, 4, 2; while (!new_value( )); v1 = read_value( ); if (v1 != c[1]) then error = 1; while (!new_value( )); v2 = read_value( ); if (v2 != c[2]) then error = 1; while (!new_value( )); v3 = read_value( ); if (v2 != c[3]) then error = 1; if (error == 1) then return(0); else return (1); }

CS Fall 2005 – Lecture #29: Recap - 7 Implementation as a sequential digital system zEncoding: yhow many bits per input value? yhow many values in sequence? yhow do we know a new input value is entered? yhow do we represent the states of the system? zBehavior: yclock wire tells us when it’s ok to look at inputs (i.e., they have settled after change) ysequential: sequence of values must be entered ysequential: remember if an error occurred yfinite-state specification reset value open/closed new clock state

CS Fall 2005 – Lecture #29: Recap - 8 closed C1=value & new C2=value & new C3=value & new C1!=value & new C2!=value & new C3!=value & new closed reset not new S1S2S3OPEN ERR open Sequential example (cont’d): abstract control zFinite-state diagram yStates: 5 states xrepresent point in execution of machine xeach state has outputs yTransitions: 6 from state to state, 5 self transitions, 1 global xchanges of state occur when clock says it’s ok xbased on value of inputs yInputs: reset, new, results of comparisons yOutput: open/closed

CS Fall 2005 – Lecture #29: Recap - 9 reset open/closed new C1C2C3 comparator value equal multiplexer equal controller mux control clock Sequential example (cont’d): data-path vs. control zInternal structure ydata-path xstorage for combination xcomparators ycontrol xfinite-state machine controller xcontrol for data-path xstate changes controlled by clock

CS Fall 2005 – Lecture #29: Recap - 10 closed mux=C1 reset equal & new not equal & new not new S1S2S3OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open Sequential example (cont’d): finite-state machine zFinite-state machine yrefine state diagram to include internal structure

CS Fall 2005 – Lecture #29: Recap - 11 resetnewequalstatestatemuxopen/closed 1–––S1C1closed 00–S1S1C1closed 010S1ERR–closed 011S1S2C2closed 00–S2S2C2closed 010S2ERR–closed 011S2S3C3closed 00–S3S3C3closed 010S3ERR–closed 011S3OPEN–open 0 – –OPENOPEN– open 0 – –ERRERR– closed next Sequential example (cont’d): finite-state machine zFinite-state machine ygenerate state table (much like a truth-table) closed mux=C1 reset equal & new not equal & new not new S1S2S3OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open

CS Fall 2005 – Lecture #29: Recap - 12 Sequential example (cont’d): encoding zEncode state table ystate can be: S1, S2, S3, OPEN, or ERR xneeds at least 3 bits to encode: 000, 001, 010, 011, 100 xand as many as 5: 00001, 00010, 00100, 01000, xchoose 4 bits: 0001, 0010, 0100, 1000, 0000 youtput mux can be: C1, C2, or C3 xneeds 2 to 3 bits to encode xchoose 3 bits: 001, 010, 100 youtput open/closed can be: open or closed xneeds 1 or 2 bits to encode xchoose 1 bits: 1, 0

CS Fall 2005 – Lecture #29: Recap - 13 good choice of encoding! mux is identical to last 3 bits of state open/closed is identical to first bit of state Sequential example (cont’d): encoding zEncode state table ystate can be: S1, S2, S3, OPEN, or ERR xchoose 4 bits: 0001, 0010, 0100, 1000, 0000 youtput mux can be: C1, C2, or C3 xchoose 3 bits: 001, 010, 100 youtput open/closed can be: open or closed xchoose 1 bits: 1, 0 resetnewequalstatestatemuxopen/closed 1––– – – – – – – – 1 0 – – – 1 0 – – – 0 next

CS Fall 2005 – Lecture #29: Recap - 14 reset open/closed newequal controller mux control clock reset open/closed newequal mux control clock comb. logic state special circuit element, called a register, for remembering inputs when told to by clock Sequential example (cont’d): controller implementation zImplementation of the controller

CS Fall 2005 – Lecture #29: Recap - 15 digital system data-path control state registers combinational logic multiplexer comparator code registers registerlogic switching networks Design hierarchy

CS Fall 2005 – Lecture #29: Recap - 16 Design methodology HDL Specification Structure and Function (Behavior) of a Design Simulation Verification: Design Behave as Required? Functional: I/O Behavior Register-Level (Architectural) Logic-Level (Gates) Transistor-Level (Electrical) Timing: Waveform Behavior Synthesis Generation: Map Specification to Implementation

CS Fall 2005 – Lecture #29: Recap - 17 Combinational Logic Implementation zK-map method to map truth tables into minimized gate level descriptions zAlternative implementation approaches: yTwo-level logic, multi-level logic, logic implementation with multiplexers yProgrammable logic in the form of PLAs, ROMs, Muxes, … yField programmable logic in the form of devices like Xilinx zCombinational logic building blocks yArithmetic and logic units, including adders/subtractors and other arithmetic functions (e.g., combinational multipliers)

CS Fall 2005 – Lecture #29: Recap - 18 Sequential Logic Implementation zModels for representing sequential circuits yAbstraction of sequential elements yFinite state machines and their state diagrams yInputs/outputs yMealy, Moore, and synchronous Mealy machines zFinite state machine design procedure yDeriving state diagram yDeriving state transition table yDetermining next state and output functions yImplementing combinational logic zSequential logic building blocks yRegisters, Register files (with multiple read and write ports), Shifters, Counters, RAMs yArbitrators

CS Fall 2005 – Lecture #29: Recap - 19 State Machine Implementation zPartitioned State Machines yWays to organize single complex monolithic state machine into simpler, interacting state machines based on functional partitioning xTime state approach offers one conceptual method xMuch more relevant is what you likely did in your course project zIssues of synchronization across independently clocked subsystems ySynchronization of signals yFour cycle handshake

CS Fall 2005 – Lecture #29: Recap - 20 Final Exam zExam Group 12 zFriday, December 16, 5:00-8:00 PM zRoom: Bechtel Auditorium

CS Fall 2005 – Lecture #29: Recap - 21 Final Exam z(Long) Design Specification in English for an “interesting” digital subsystem yFunction described in terms of desired input/output behavior yYou will need to be able to hand generate waveform diagrams to demonstrate that you understand the design specification! zYou will have to partition the subsystem into control and datapath yDesign the control part as one or more interacting Finite State Machines xState Diagrams as well as Verilog for control yDesign the datapath blocks xBehavioral Verilog mostly, but gate level hand-drawn schematics for some selected parts zYou will have to revise the design to improve its performance

CS Fall 2005 – Lecture #29: Recap - 22 Final Exam zThe Exam is conceptual and DESIGN-skills oriented zThe Exam is not about obscure details of technologies like the Xilinx or Actel internal architectures zThe best way to study for The Exam is to review your course project and to reflect on the process you went through in designing and implementing it! zThe Exam design problem won’t be an Etch-a-Sketch—it will be some kind of digital system with control and a datapath that can be specified in a couple of pages of English text! zYou will need to write a lot for this Exam! Bring multiple pencils, erasers, rulers, AND AT LEAST TWO BLUE BOOKs!!! You won’t need a computer or a calculator! zOpen course textbook and open course notes. They probably won’t help you much ;-)